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1. WO2015015923 - ワイドバンドギャップ半導体装置

公開番号 WO/2015/015923
公開日 05.02.2015
国際出願番号 PCT/JP2014/065713
国際出願日 13.06.2014
IPC
H01L 29/06 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
29整流,増幅,発振またはスイッチングに特に適用される半導体装置であり,少なくとも1つの電位障壁または表面障壁を有するもの;少なくとも1つの電位障壁または表面障壁,例.PN接合空乏層またはキャリア集中層,を有するコンデンサーまたは抵抗器;半導体本体または電極の細部
02半導体本体
06半導体本体の形状に特徴のあるもの;半導体領域の形状,相対的な大きさまたは配列に特徴のあるもの
H01L 21/336 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
18不純物,例.ドーピング材料,を含むまたは含まない周期表第IV族の元素またはA↓I↓I↓IB↓V化合物から成る半導体本体を有する装置
334ユニポーラ型の装置の製造のための多段階工程
335電界効果トランジスタ
336絶縁ゲートを有するもの
H01L 29/12 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
29整流,増幅,発振またはスイッチングに特に適用される半導体装置であり,少なくとも1つの電位障壁または表面障壁を有するもの;少なくとも1つの電位障壁または表面障壁,例.PN接合空乏層またはキャリア集中層,を有するコンデンサーまたは抵抗器;半導体本体または電極の細部
02半導体本体
12構成材料に特徴のあるもの
H01L 29/78 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
29整流,増幅,発振またはスイッチングに特に適用される半導体装置であり,少なくとも1つの電位障壁または表面障壁を有するもの;少なくとも1つの電位障壁または表面障壁,例.PN接合空乏層またはキャリア集中層,を有するコンデンサーまたは抵抗器;半導体本体または電極の細部
66半導体装置の型
68整流,増幅またはスイッチされる電流を流さない電極に電流のみまたは電位のみを与えることにより制御できるもの
76ユニポーラ装置
772電界効果トランジスタ
78絶縁ゲートによって生じる電界効果を有するもの
CPC
H01L 29/0615
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0611for increasing or controlling the breakdown voltage of reverse biased devices
0615by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
H01L 29/0619
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0611for increasing or controlling the breakdown voltage of reverse biased devices
0615by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
0619with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
H01L 29/0638
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0638for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
H01L 29/0649
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0642Isolation within the component, i.e. internal isolation
0649Dielectric regions, e.g. SiO2 regions, air gaps
H01L 29/0661
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0657characterised by the shape of the body
0661specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
H01L 29/1602
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
12characterised by the materials of which they are formed
16including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
1602Diamond
出願人
  • 住友電気工業株式会社 SUMITOMO ELECTRIC INDUSTRIES, LTD. [JP/JP]; 大阪府大阪市中央区北浜四丁目5番33号 5-33, Kitahama 4-chome, Chuo-ku, Osaka-shi, Osaka 5410041, JP
発明者
  • 増田 健良 MASUDA, Takeyoshi; JP
代理人
  • 特許業務法人深見特許事務所 FUKAMI PATENT OFFICE, P.C.; 大阪府大阪市北区中之島二丁目2番7号 中之島セントラルタワー Nakanoshima Central Tower, 2-7, Nakanoshima 2-chome, Kita-ku, Osaka-shi, Osaka 5300005, JP
優先権情報
2013-16060801.08.2013JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) WIDE-BANDGAP SEMICONDUCTOR ELEMENT
(FR) ÉLÉMENT À SEMI-CONDUCTEUR À LARGE BANDE INTERDITE
(JA) ワイドバンドギャップ半導体装置
要約
(EN)
This wide-bandgap semiconductor element is provided with a semiconductor substrate (epitaxial substrate) (20) that has a principal surface (top surface) (P2) and comprises a wide-bandgap semiconductor. Said semiconductor substrate (20) has a device region (20E) and a surrounding region (20T) surrounding said device region (20E). In the surrounding region (20T), the semiconductor substrate (20) has a first semiconductor region (drift layer) (21) that has a first conductivity type and a second semiconductor region (field-limiting region) (25) that is formed on top of the first semiconductor region (drift layer) (21), has a principal surface (P2), and has a second conductivity type that is different from the first conductivity type. The principal surface (P2) of the second semiconductor region (field-limiting region) (25) has a plurality of grooves (70) that form rings around the device region (20E). This makes it possible to provide a wide-bandgap semiconductor element that exhibits an increased breakdown voltage without an increase in size.
(FR)
La présente invention concerne un élément à semi-conducteur à large bande interdite qui comprend un substrat semi-conducteur (substrat épitaxial) (20) qui présente une surface principale (surface supérieure) (P2) et comprend un semi-conducteur à large bande interdite. Ledit substrat semi-conducteur (20) comprend une région de dispositif (20E) et une région environnante (20T) entourant ladite région de dispositif (20E). Dans la région environnante (20T), le substrat semi-conducteur (20) comprend une première région semi-conductrice (couche de migration) (21) qui possède un premier type de conductivité et une seconde région semi-conductrice (région de limitation de champ) (25) qui est formée au-dessus de la première région semi-conductrice (couche de migration) (21), présente une surface principale (P2) et possède un second type de conductivité qui est différent du premier type de conductivité. La surface principale (P2) de la seconde région semi-conductrice (région de limitation de champ) (5) comporte une pluralité de rainures (70) qui forment des anneaux autour de la région de dispositif (20E). Cela permet de produire un élément à semi-conducteur à large bande interdite qui offre une tension de claquage accrue sans augmentation de taille.
(JA)
 主面(上部表面)(P2)を有し、ワイドバンドギャップ半導体からなる半導体基板(エピタキシャル基板)(20)を備え、半導体基板(20)は、半導体基板(20)に形成されたデバイス領域(20E)と、デバイス領域(20E)を囲むように形成された周辺領域(20T)とを含む。周辺領域(20T)において、半導体基板(20)は、第1の導電型を有する第1の半導体領域(ドリフト層)(21)と、第1の半導体領域(ドリフト層)(21)上に形成され、主面(P2)を有し、第1の導電型と異なる第2の導電型を有する第2の半導体領域(電界緩和領域)(25)とを含み、第2の半導体領域(電界緩和領域)(25)の主面(P2)には、デバイス領域(20E)を環状に囲む複数の溝(70)が形成されている。これにより、サイズを大きくすることなく、高耐圧化することができるワイドバンドギャップ半導体装置を提供する。
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