ご意見送信
設定

設定

出願の表示

1. WO2014175133 - 半導体装置及びその製造方法

パーマリンク
公開番号 WO/2014/175133
公開日 30.10.2014
国際出願番号 PCT/JP2014/060794
国際出願日 16.04.2014
IPC
H01L 25/065 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
25複数の個々の半導体または他の固体装置からなる組立体
03すべての装置がグループH01L27/00~H01L51/00の同じサブグループに分類される型からなるもの,例.整流ダイオードの組立体
04個別の容器を持たない装置
065装置がグループH01L27/00に分類された型からなるもの
H01L 23/29 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
28封緘,例.封緘層,被覆
29材料に特徴のあるもの
H01L 23/31 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
28封緘,例.封緘層,被覆
31配列に特徴のあるもの
H01L 25/07 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
25複数の個々の半導体または他の固体装置からなる組立体
03すべての装置がグループH01L27/00~H01L51/00の同じサブグループに分類される型からなるもの,例.整流ダイオードの組立体
04個別の容器を持たない装置
07装置がグループH01L29/00に分類された型からなるもの
H01L 25/18 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
25複数の個々の半導体または他の固体装置からなる組立体
18装置がグループH01L27/00~H01L51/00の同じメイングループの2つ以上の異なるサブグループに分類される型からなるもの
CPC
H01L 21/31053
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
31051Planarisation of the insulating layers
31053involving a dielectric removal step
H01L 21/4853
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4846Leads on or in insulating or insulated substrates, e.g. metallisation
4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
H01L 21/56
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
H01L 2224/11334
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
11Manufacturing methods
113by local deposition of the material of the bump connector
1133in solid form
11334using preformed bumps
H01L 2224/13025
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
1302Disposition
13025the bump connector being disposed on a via connection of the semiconductor or solid-state body
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
出願人
  • ピーエスフォー　ルクスコ　エスエイアールエル PS4 LUXCO S.A.R.L. [LU]/[LU]
  • 山口　昌浩 YAMAGUCHI Masahiro [JP]/[JP] (US)
  • 嵯峨　徹 SAGA Toru [JP]/[JP] (US)
  • 細川　浩二 HOSOKAWA Koji [JP]/[JP] (US)
発明者
  • 山口　昌浩 YAMAGUCHI Masahiro
  • 嵯峨　徹 SAGA Toru
  • 細川　浩二 HOSOKAWA Koji
代理人
  • 鷲頭　光宏 WASHIZU Mitsuhiro
優先権情報
2013-09067723.04.2013JP
公開言語 (言語コード) 日本語 (ja)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
front page image
要約
(EN) [Problem] To provide a semiconductor device suitable for use as an upper-side package of a semiconductor device having a PoP structure. [Solution] This invention is provided with a semiconductor chip (10) flip-chip mounted on one surface (32) of a wiring board (30), and a semiconductor chip (20) flip-chip mounted on the other surface (33) of the wiring board (30), the semiconductor chips (10, 20) being installed in directions that differ by 90°. It is thereby possible to prevent the layout of wiring patterns (41, 42) on the wiring board (30) from becoming locally congested and enhance the freedom of layout. In addition, when the semiconductor chips (10, 20) are mounted on the wiring board (30), the location at which the load concentrates can be held by a stage, thereby making it possible to prevent the wiring board from deforming.
(FR) [Problème] La présente invention concerne un dispositif semi-conducteur approprié pour être utilisé en tant que boîtier supérieur d'un dispositif semi-conducteur ayant une structure PoP. [Solution] La présente invention propose une puce à semi-conducteur (10) montée en technique flip-chip sur une surface (32) d'une carte à circuits imprimés (30), et une puce à semi-conducteur (20) montée en technique flip-chip sur l'autre surface (33) de la carte à circuits imprimés (30), les puces à semi-conducteur (10, 20) étant installées dans des directions qui diffèrent de 90° l'une de l'autre. Il est donc possible d'empêcher la congestion locale de l'implantation de motifs de câblage (41, 42) sur la carte à circuits imprimés (30) et d'améliorer la liberté d'implantation. De plus, lorsque les puces à semi-conducteur (10, 20) sont montées sur la carte à circuits imprimés (30), la position à laquelle la charge se concentre peut être maintenue par une platine, ce qui permet d'empêcher la déformation de la carte à circuits imprimés.
(JA) 【課題】ＰｏＰ構造を有する半導体装置の上側パッケージとしての利用が好適な半導体装置を提供する。 【解決手段】配線基板３０の一面３２にフリップチップ実装された半導体チップ１０と、配線基板３０の他面３３にフリップチップ実装された半導体チップ２０とを備え、これら半導体チップ１０，２０の搭載方向が互いに９０°異なっている。これにより、配線基板３０上における配線パターン４１，４２のレイアウトが局所的に密集することが無く、レイアウトの自由度を高めることが可能となる。しかも、半導体チップ１０，２０を配線基板３０に実装する際、荷重が集中する位置をステージによって保持することができるため、配線基板に生じる変形を防止することが可能となる。
関連特許文献
US20160079207
国際事務局に記録されている最新の書誌情報
# -