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出願の表示

1. WO2014141399 - 半導体装置

公開番号 WO/2014/141399
公開日 18.09.2014
国際出願番号 PCT/JP2013/056925
国際出願日 13.03.2013
IPC
H01L 21/52 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
50サブグループH01L21/06~H01L21/326の一つに分類されない方法または装置を用いる半導体装置の組立
52容器中への半導体本体のマウント
CPC
H01L 2224/26175
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
2612Auxiliary members for layer connectors, e.g. spacers
26152being formed on an item to be connected not being a semiconductor or solid-state body
26175Flow barriers
H01L 2224/29036
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
2902Disposition
29034the layer connector covering only portions of the surface to be connected
29036covering only the central area of the surface to be connected
H01L 2224/291
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29099Material
291with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
H01L 2224/32014
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
3201Structure
32012relative to the bonding area, e.g. bond pad
32014the layer connector being smaller than the bonding area, e.g. bond pad
H01L 2224/32113
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32113the whole layer connector protruding from the surface
H01L 2224/32245
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32245the item being metallic
出願人
  • トヨタ自動車株式会社 TOYOTA JIDOSHA KABUSHIKI KAISHA [JP]/[JP] (AllExceptUS)
  • 織本 憲宗 ORIMOTO Norimune [JP]/[JP] (US)
  • 今井 誠 IMAI Makoto [JP]/[JP] (US)
発明者
  • 織本 憲宗 ORIMOTO Norimune
  • 今井 誠 IMAI Makoto
代理人
  • 特許業務法人 快友国際特許事務所 KAI-U PATENT LAW FIRM
優先権情報
公開言語 (言語コード) 日本語 (ja)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
要約
(EN)  Disclosed is a semiconductor device. This semiconductor device includes a semiconductor element that has a rectangular shape in a plan view, and a fixing member to which the semiconductor element is fixed. The semiconductor element is disposed such that the rectangular surface thereof faces the surface of the fixing member. Part of the rectangular surface of the semiconductor element is fixed to the surface of the fixing member, and at least the corners of the rectangular surface are not fixed to the surface of the fixing member. In this semiconductor device, the fixing member and the corners of the semiconductor element, which are more susceptible to thermal stress occurring when the temperature of the semiconductor device changes, are not fixed to each other. It is thus possible to reduce thermal stress in the semiconductor element. It is also possible to suppress an increase in the size of the semiconductor device by simply using a configuration in which the fixing member and the corners of the semiconductor element are not fixed to each other.
(FR) La présente invention se rapporte à un dispositif à semi-conducteur. Le dispositif à semi-conducteur comprend un élément semi-conducteur qui présente une forme rectangulaire selon une vue en plan, et un élément de fixation auquel l'élément semi-conducteur est fixé. L'élément semi-conducteur est disposé de telle sorte que la surface rectangulaire de ce dernier soit orientée vers la surface de l'élément de fixation. Une partie de la surface rectangulaire de l'élément semi-conducteur est fixée à la surface de l'élément de fixation, et au moins les coins de la surface rectangulaire ne sont pas fixés à la surface de l'élément de fixation. Dans ce dispositif à semi-conducteur, l'élément de fixation et les coins de l'élément semi-conducteur, qui sont plus sensibles à une contrainte thermique qui se produit lorsque la température du dispositif à semi-conducteur change, ne sont pas fixés les uns aux autres. Ainsi, il est possible de réduire la contrainte thermique dans l'élément semi-conducteur. Il est également possible de supprimer une augmentation de la taille du dispositif à semi-conducteur en utilisant simplement une configuration dans laquelle l'élément de fixation et les coins de l'élément semi-conducteur ne sont pas fixés les uns aux autres.
(JA)  本明細書は、半導体装置を開示する。その半導体装置は、平面視すると矩形状の半導体素子と、半導体素子が固定される被固定部材と、を備えている。半導体素子は、その矩形状の面を被固定部材の表面に向けて配置されている。半導体素子の矩形状の面は、一部において被固定部材の表面に固定されており、該矩形状の面の少なくとも角部は、被固定部材の表面に固定されていない。上記の半導体装置では、半導体装置の温度が変化した場合に熱応力が生じ易い半導体素子の角部と、被固定部材とが互いに固定されていない。これにより、半導体素子に生じる熱応力を低減することができる。また、半導体素子の角部と被固定部材とが互いに固定されない構成とするだけなので、半導体装置の体格の増大を抑制することができる。
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