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1. WO2014136636 - 薄膜トランジスタ

公開番号 WO/2014/136636
公開日 12.09.2014
国際出願番号 PCT/JP2014/054739
国際出願日 26.02.2014
IPC
H01L 29/786 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
29整流,増幅,発振またはスイッチングに特に適用される半導体装置であり,少なくとも1つの電位障壁または表面障壁を有するもの;少なくとも1つの電位障壁または表面障壁,例.PN接合空乏層またはキャリア集中層,を有するコンデンサーまたは抵抗器;半導体本体または電極の細部
66半導体装置の型
68整流,増幅またはスイッチされる電流を流さない電極に電流のみまたは電位のみを与えることにより制御できるもの
76ユニポーラ装置
772電界効果トランジスタ
78絶縁ゲートによって生じる電界効果を有するもの
786薄膜トランジスタ
H01L 21/336 2006.1
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
18不純物,例.ドーピング材料,を含むまたは含まない周期表第IV族の元素またはA↓I↓I↓IB↓V化合物から成る半導体本体を有する装置
334ユニポーラ型の装置の製造のための多段階工程
335電界効果トランジスタ
336絶縁ゲートを有するもの
CPC
H01L 27/1292
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1259Multistep manufacturing methods
1292using liquid deposition, e.g. printing
H01L 29/0692
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0684characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
0692Surface layout
H01L 29/41733
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
417carrying the current to be rectified, amplified or switched
41725Source or drain electrodes for field effect devices
41733for thin film transistors with insulated gate
H01L 29/42384
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42384for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
H01L 29/4908
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
4908for thin film semiconductor, e.g. gate of TFT
H01L 29/78603
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
786Thin film transistors, ; i.e. transistors with a channel being at least partly a thin film
78603characterised by the insulating substrate or support
出願人
  • 住友化学株式会社 SUMITOMO CHEMICAL COMPANY, LIMITED [JP]/[JP]
  • 国立大学法人大阪大学 OSAKA UNIVERSITY [JP]/[JP]
発明者
  • 岡地 崇之 OKACHI, Takayuki
  • 竹谷 純一 TAKEYA, Junichi
代理人
  • 酒井 宏明 SAKAI, Hiroaki
優先権情報
2013-04470806.03.2013JP
公開言語 (言語コード) 日本語 (ja)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) THIN FILM TRANSISTOR
(FR) TRANSISTOR EN COUCHES MINCES
(JA) 薄膜トランジスタ
要約
(EN) A thin film transistor which has higher On-state current and On/Off ratio and can be driven at a lower voltage. A thin film transistor (10) is provided with: a columnar projection (8) which has a lateral surface (2a) and protrudes from the main surface of a substrate; a gate insulating layer (4), at least a part of which is provided in a channel region (CR) that extends along the lateral surface, and which contains a first layer (4a) and a second layer (4b) and has a thickness of 50 nm or less; a gate electrode (3) which is in contact with the gate insulating layer; a source electrode (5) and a drain electrode (6), which are separated from each other, and one of which is provided so as to at least partially overlap the projection, while the other being provided in a region that does not overlap the projection and the one electrode; and a semiconductor layer (7) which is in contact with at least a part of the source electrode, at least a part of the drain electrode and at least a part of the gate insulating layer within the channel region directly or with a functional layer being interposed therebetween.
(FR) L'invention concerne un transistor en couches minces qui possède un courant d'état allumé et un rapport allumé/éteint supérieurs et qui peut être attaqué à une tension inférieure. Un transistor en couches minces (10) comprend : une saillie en colonne (8) qui possède une surface latérale (2a) et qui fait saillie à partir de la surface principale d'un substrat ; une couche d'isolation de grille (4), au moins une partie de laquelle étant disposée dans une région de canal (CR) qui s'étend le long de la surface latérale, et qui contient une première couche (4a) et une seconde couche (4b) et qui possède une épaisseur de 50 nm ou moins ; une électrode de grille (3) qui est en contact avec la couche d'isolation de grille ; une électrode de source (5) et une électrode de drain (6), qui sont séparées les unes des autres, et dont l'une est disposée de façon à recouvrir partiellement la saillie, alors que l'autre est disposée dans une région qui ne recouvre pas la saillie et ladite une électrode ; et une couche de semi-conducteur (7) qui est en contact avec au moins une partie de l'électrode de source, au moins une partie de l'électrode de drain et au moins une partie de la couche d'isolation de grille dans la région de canal directement ou avec une couche fonctionnelle interposée entre celles-ci.
(JA)  より高いオン電流及びオン/オフ比を有し、より低電圧で駆動できる薄膜トランジスタ。薄膜トランジスタ(10)は、側面(2a)を有し、基板の主表面から突出する柱状の突出部(8)と、側面に沿って延在するチャネル領域CRに少なくとも一部が設けられており、第1の層(4a)及び第2の層(4b)を含む、厚さが50nm以下であるゲート絶縁層(4)と、ゲート絶縁層に接しているゲート電極(3)と、ソース電極(5)及びドレイン電極(6)の一方のうちの少なくとも一部が突出部と重なるように設けられており、他方が突出部及び一方の電極と重ならない領域に設けられており、かつ互いに分離されているソース電極及びドレイン電極と、ソース電極のうちの少なくとも一部、ドレイン電極のうちの少なくとも一部、及びチャネル領域内のゲート絶縁層のうちの少なくとも一部に直接的に又は機能層を介して接している半導体層(7)とを備える。
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