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1. WO2013105331 - 半導体装置及びその製造方法

公開番号 WO/2013/105331
公開日 18.07.2013
国際出願番号 PCT/JP2012/078881
国際出願日 07.11.2012
IPC
H01L 21/336 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
18不純物,例.ドーピング材料,を含むまたは含まない周期表第IV族の元素またはA↓I↓I↓IB↓V化合物から成る半導体本体を有する装置
334ユニポーラ型の装置の製造のための多段階工程
335電界効果トランジスタ
336絶縁ゲートを有するもの
H01L 29/78 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
29整流,増幅,発振またはスイッチングに特に適用される半導体装置であり,少なくとも1つの電位障壁または表面障壁を有するもの;少なくとも1つの電位障壁または表面障壁,例.PN接合空乏層またはキャリア集中層,を有するコンデンサーまたは抵抗器;半導体本体または電極の細部
66半導体装置の型
68整流,増幅またはスイッチされる電流を流さない電極に電流のみまたは電位のみを与えることにより制御できるもの
76ユニポーラ装置
772電界効果トランジスタ
78絶縁ゲートによって生じる電界効果を有するもの
CPC
H01L 21/2254
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; ; Interactions between two or more impurities; Redistribution of impurities
225using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
2251Diffusion into or out of group IV semiconductors
2254from or through or into an applied layer, e.g. photoresist, nitrides
H01L 29/16
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
12characterised by the materials of which they are formed
16including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
H01L 29/47
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
47Schottky barrier electrodes
H01L 29/66477
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
H01L 29/665
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
665using self aligned silicidation, i.e. salicide
H01L 29/66643
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66568Lateral single gate silicon transistors
66643with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
出願人
  • 株式会社東芝 KABUSHIKI KAISHA TOSHIBA [JP]/[JP]
発明者
  • 小池 正浩 KOIKE, Masahiro
  • 上牟田 雄一 KAMIMUTA, Yuuichi
  • 手塚 勉 TEZUKA, Tsutomu
代理人
  • 蔵田 昌俊 KURATA, Masatoshi
優先権情報
2012-00309511.01.2012JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
要約
(EN)
A semiconductor device is used in a low-power-consumption LSI, and is provided with: a first conductivity-type semiconductor substrate (10) having Ge as a main component; a pair of metal semiconductor compound layers (14) provided apart from each other in a surface portion of the substrate (10); and a gate electrode (12) provided on a region sandwiched between the metal semiconductor compound layers (14) of the substrate (10) with a gate insulating film (11) therebetween. A second conductivity-type impurity diffused region in which at least two types of impurities of a chalcogen element and a second conductivity-type impurity element are doped is formed in the vicinity of an interface between the compound layers (14) and the substrate (10). The concentration distribution of the second conductivity-type impurity in the vicinity of the interface has, in the order from the interface to the substrate (10) side, a first region in which the concentration distribution abruptly changes, a second region in which the concentration distribution gently changes, and a third region in which the concentration distribution abruptly changes.
(FR)
La présente invention concerne un dispositif à semi-conducteur utilisé dans un LSI à faible consommation d'énergie, et comportant : un substrat semi-conducteur d'un premier type de conductivité (10) ayant Ge en tant que composant principal; une paire de couches de composé semi-conducteur métallique (14) qui sont disposées de manière séparée l'une de l'autre dans une partie de surface du substrat (10); et une électrode de grille (12) disposée sur une région prise en sandwich entre les couches de composé semi-conducteur métallique (14) du substrat (10) comportant un film isolant de grille (11) entre elles. Une région de diffusion d'impuretés d'un second type de conductivité, dans laquelle au moins deux types d'impuretés d'un élément de chalcogène et d'un élément d'impureté d'un second type de conductivité sont dopés, est formée à proximité d'une interface entre les couches de composé (14) et le substrat (10). La distribution de concentration de l'impureté du second type de conductivité à proximité de l'interface comporte, dans l'ordre allant de l'interface jusqu'au côté substrat (10), une première région dans laquelle la distribution de concentration change brusquement, une deuxième région dans laquelle la distribution de concentration change modérément, et une troisième région dans laquelle la distribution de concentration change brusquement.
(JA)
 低消費電力LSIに利用される半導体装置であって、Geを主成分とする第1導電型の半導体基板(10)と、基板(10)の表面部に離間して設けられた一対の金属半導体化合物層(14)と、基板(10)の金属半導体化合物層(14)により挟まれた領域上にゲート絶縁膜(11)を介して設けられたゲート電極(12)とを備えている。化合物層(14)と基板(10)との界面付近に、カルコゲン元素と、第2導電型不純物元素との少なくとも二種の不純物が導入された第2導電型の不純物拡散領域が形成されている。界面付近の第2導電型不純物の濃度分布は、界面から基板(10)側に離れる順に、急峻に変化する第1の領域と、なだらかに変化する第2の領域と、急峻に変化する第3の領域とを有する。
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