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1. WO2013080790 - 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体

公開番号 WO/2013/080790
公開日 06.06.2013
国際出願番号 PCT/JP2012/079463
国際出願日 14.11.2012
IPC
H05K 3/46 2006.01
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
46多重層回路の製造
CPC
H01L 21/4857
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4846Leads on or in insulating or insulated substrates, e.g. metallisation
4857Multilayer substrates
H01L 2224/02311
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0231Manufacturing methods of the redistribution layers
02311Additive methods
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/04105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
H01L 2224/05569
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05569the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
H01L 2224/08237
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
081Disposition
0812the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
08151the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
08221the body and the item being stacked
08225the item being non-metallic, e.g. insulating substrate with or without metallisation
08237the bonding area connecting to a bonding area disposed in a recess of the surface of the item
出願人
  • 株式会社フジクラ FUJIKURA LTD. [JP]/[JP]
発明者
  • 糸井 和久 ITOI, Kazuhisa
  • 岡本 誠裕 OKAMOTO, Masahiro
代理人
  • 伊丹 勝 ITAMI, Masaru
優先権情報
2011-26221730.11.2011JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) BOARD WITH EMBEDDED COMPONENT AND METHOD FOR MANUFACTURING SAME, AND PACKAGE WITH BOARD WITH EMBEDDED COMPONENT
(FR) CARTE À COMPOSANT INCORPORÉ ET SON PROCÉDÉ DE FABRICATION, ET CONDITIONNEMENT AVEC CARTE À COMPOSANT INCORPORÉ
(JA) 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体
要約
(EN)
A package with a board with an embedded component (100) comprises a board with an embedded component (1), and a mounting board (2) on which the board with the embedded component is mounted. The board with the embedded component (1) is provided with a structure wherein second to fourth printed wiring substrates (20-40) and a cover lay film (3) are laminated in a package by thermocompression bonding. Inside an open part (29) formed in a second resin substrate (21) of the second printed wiring substrate (20), the back (91a) of an electronic component (90) and a heat-conducting layer (23A) are bonded and embedded in a fixed state by an adhesion layer (9) with holes (23B) therebetween. Bumps (49) are formed on a mounting surface (2a) side of the fourth printed wiring substrate (40). Heat from the electronic component (90): passes through thermal vias and thermal wiring of each layer via thermal vias (24) and the heat-conducting layers (23A), which are in contact with the back (91a) of the electronic component (90); is transmitted from the bumps (49) to the mounting board (2); and is dissipated via the mounting board (2).
(FR)
Le conditionnement selon l'invention avec une carte à composant incorporé (100) comprend une carte comportant un composant incorporé (1), et une carte de montage (2) sur laquelle la carte comportant le composant incorporé est montée. La carte comportant le composant incorporé (1) comporte une structure dans laquelle des deuxième à quatrième substrats de circuit imprimé (20, 30, 40) et une pellicule de recouvrement (3) sont stratifiés dans un conditionnement par soudage par thermocompression. À l'intérieur d'une partie ouverte (29) formée dans un deuxième substrat de résine (21) du deuxième substrat de circuit imprimé (20), l'arrière (91a) d'un composant électronique (90) et une couche conductrice de chaleur (23A) sont soudés et incorporés dans un état fixe par une couche d'adhésion (9) avec des trous (23B) entre eux. Des globules (49) sont formés sur un côté de surface de montage (2a) du quatrième substrat de circuit imprimé (40). La chaleur du composant électronique (90) : traverse des interconnexions thermiques et le circuit thermique de chaque couche via des interconnexions thermiques (24) et les couches conductrices de chaleur (23A), lesquelles sont en contact avec l'arrière (91a) du composant électronique (90); est transmise des globules (49) à la carte de montage (2); et est dissipée via la carte de montage (2).
(JA)
部品内蔵基板実装体(100)は、部品内蔵基板(1)と、これが実装された実装基板(2)とからなる。部品内蔵基板(1)は、第2~第4プリント配線基材(20)~(40)及びカバーレイフィルム(3)を熱圧着により一括積層した構造を備える。第2プリント配線基材(20)の第2樹脂基材(21)に形成された開口部(29)内には、電子部品(90)の裏面(91a)と導熱層(23A)とが密着し、且つ孔部(23B)を介して接着層(9)により固定された状態で内蔵されている。第4プリント配線基材(40)の実装面(2a)側にはバンプ(49)が形成されている。電子部品(90)の裏面(91a)に接する導熱層(23A)やサーマルビア(24)を介して、各層のサーマルビア及びサーマル配線を通り、バンプ(49)から実装基板(2)に電子部品(90)の熱が伝わって、実装基板(2)にて放熱される。
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