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1. WO2013008552 - 電子部品内蔵配線板及びその製造方法

公開番号 WO/2013/008552
公開日 17.01.2013
国際出願番号 PCT/JP2012/063956
国際出願日 30.05.2012
IPC
H05K 3/46 2006.01
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
46多重層回路の製造
H01L 23/12 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
12マウント,例.分離できない絶縁基板
H05K 1/11 2006.01
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
1印刷回路
02細部
11印刷回路への,または印刷回路間の電気的接続のための印刷要素
CPC
H01L 2224/16227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
16227the bump connector connecting to a bond pad of the item
H01L 2224/24
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
18High density interconnect [HDI] connectors; Manufacturing methods related thereto
23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
24of an individual high density interconnect connector
H01L 23/49822
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49822Multilayer substrates
H01L 23/49827
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
H01L 23/50
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
50for integrated circuit devices, ; e.g. power bus, number of leads
H01L 2924/3511
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
30Technical effects
35Mechanical effects
351Thermal stress
3511Warping
出願人
  • イビデン株式会社 IBIDEN CO., LTD. [JP]/[JP] (AllExceptUS)
  • 清水 敬介 SHIMIZU Keisuke [JP]/[JP] (UsOnly)
  • 三門 幸信 MIKADO Yukinobu [JP]/[JP] (UsOnly)
  • 酒井 俊輔 SAKAI Shunsuke [JP]/[JP] (UsOnly)
  • 冨川 満広 TOMIKAWA Mitsuhiro [JP]/[JP] (UsOnly)
  • 古谷 俊樹 FURUTANI Toshiki [JP]/[JP] (UsOnly)
発明者
  • 清水 敬介 SHIMIZU Keisuke
  • 三門 幸信 MIKADO Yukinobu
  • 酒井 俊輔 SAKAI Shunsuke
  • 冨川 満広 TOMIKAWA Mitsuhiro
  • 古谷 俊樹 FURUTANI Toshiki
代理人
  • 木村 満 KIMURA Mitsuru
優先権情報
2011-15527713.07.2011JP
2011-15527813.07.2011JP
2011-22086505.10.2011JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) WIRING BOARD INCORPORATING ELECTRONIC COMPONENT, AND METHOD FOR MANUFACTURING WIRING BOARD INCORPORATING ELECTRONIC COMPONENT
(FR) CARTE DE CIRCUITS INCORPORANT UN COMPOSANT ÉLECTRONIQUE, AINSI QUE PROCÉDÉ DE FABRICATION D'UNE CARTE DE CIRCUITS INCORPORANT UN COMPOSANT ÉLECTRONIQUE
(JA) 電子部品内蔵配線板及びその製造方法
要約
(EN)
A wiring board (10) has: a substrate (100), which has a first surface (F1), a second surface (F2) on the reverse side of the first surface (F1), a cavity (R10) that penetrates from the first surface (F1) to the second surface (F2), and a through hole (300a); and an electronic component (200) disposed in the cavity (R10). The through hole (300a) is configured by being filled with a conductor, a through hole conductor (300b) is formed of a first conductor portion that is tapered toward the second surface (F2) from the first surface (F1), and a second conductor portion that is tapered toward the first surface (F1) from the second surface (F2), and the first conductor portion and the second conductor portion are connected to each other in the substrate (100).
(FR)
L'invention concerne une carte de circuits (10) comprenant : un substrat (100) qui possède une première surface (F1), une seconde surface (F2) du côté opposé à la première surface (F1), une cavité (R10) qui traverse entre la première surface (F1) et la seconde surface (F2) et un trou traversant (300a) ; et un composant électronique (200) placé dans la cavité (R10). Le trou traversant (300a) est configuré en le remplissant d'un conducteur, un conducteur de trou traversant (300b) est formé d'une première partie conductrice qui s'amincit à partir de la première surface (F1) en direction de la seconde surface (F2) et d'une seconde partie conductrice qui s'amincit à partir de la seconde surface (F2) en direction de la première surface (F1). La première partie conductrice et la seconde partie conductrice sont connectées entre elles dans le substrat (100).
(JA)
 配線板(10)が、第1面(F1)と、第1面(F1)とは反対側の第2面(F2)と、第1面(F1)から第2面(F2)まで貫通するキャビティ(R10)と、スルーホール(300a)と、を有する基板(100)と、キャビティ(R10)に配置される電子部品(200)と、を有する。スルーホール(300a)は導体で充填されてなり、スルーホール導体(300b)は第1面(F1)から第2面(F2)に向かって細くなっている第1導体部と第2面(F2)から第1面(F1)に向かって細くなっている第2導体部とで形成されていて、第1導体部と第2導体部とは基板(100)内でつながっている。
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