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1. WO2013005474 - 半導体装置

公開番号 WO/2013/005474
公開日 10.01.2013
国際出願番号 PCT/JP2012/061833
国際出願日 09.05.2012
IPC
H01L 25/07 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
25複数の個々の半導体または他の固体装置からなる組立体
03すべての装置がグループH01L27/00~H01L51/00の同じサブグループに分類される型からなるもの,例.整流ダイオードの組立体
04個別の容器を持たない装置
07装置がグループH01L29/00に分類された型からなるもの
H01L 25/18 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
25複数の個々の半導体または他の固体装置からなる組立体
18装置がグループH01L27/00~H01L51/00の同じメイングループの2つ以上の異なるサブグループに分類される型からなるもの
CPC
H01L 23/24
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
16Fillings or auxiliary members in containers ; or encapsulations; , e.g. centering rings
18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
24solid or gel at the normal operating temperature of the device
H01L 23/296
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
29characterised by the material ; , e.g. carbon
293Organic, e.g. plastic
296Organo-silicon compounds
H01L 23/49861
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49861Lead-frames fixed on or encapsulated in insulating substrates
H01L 23/5385
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
5385Assembly of a plurality of insulating substrates
H01L 24/32
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
H01L 25/18
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
18the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L51/00
出願人
  • 本田技研工業株式会社 HONDA MOTOR CO., LTD. [JP]/[JP] (AllExceptUS)
  • 小倉 正巳 OGURA, Masami [JP]/[JP] (UsOnly)
  • 高柳 教人 TAKAYANAGI, Takahito [JP]/[JP] (UsOnly)
  • 加藤 潤 KATO, Jun [JP]/[JP] (UsOnly)
  • 雑賀 仁 SAIKA, Hitoshi [JP]/[JP] (UsOnly)
発明者
  • 小倉 正巳 OGURA, Masami
  • 高柳 教人 TAKAYANAGI, Takahito
  • 加藤 潤 KATO, Jun
  • 雑賀 仁 SAIKA, Hitoshi
代理人
  • 特許業務法人クシブチ国際特許事務所 KUSHIBUCHI & ASSOCIATES
優先権情報
2011-14805304.07.2011JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置
要約
(EN)
To provide a semiconductor device which can be easily manufactured and is provided with excellent cooling performance. This semiconductor device is provided with: a pair of insulating boards (17, 19) in which copper circuit boards (32, 34) are respectively bonded to one surface of ceramic substrates (30, 33) and copper plates (31, 35) are respectively bonded to the other surface of the ceramic substrates (30, 33); a plate-like resin case (15) in which a signal pin (22) and lead electrodes (23, 24) are insert molded in advance; an IGBT chip (11); and an FWD chip (13). The resin case (15) is provided with an opening portion (21) that penetrates therethrough from a front surface (15A) to a back surface (15B), and the IGBT chip (11) and the FWD chip (13) are arranged side by side in this opening portion (21). The IGBT chip (11), the FWD chip (13) and the copper circuit boards (32, 34) of the insulating boards (17, 19) are bonded together using a solder in such a manner that the IGBT chip (11), the FWD chip (13) and the resin case (15) are sandwiched by the pair of insulating boards (17, 19), with the copper plates (31, 35) of the insulating boards (17, 19) being exposed.
(FR)
L'invention concerne un dispositif semi-conducteur qui peut être fabriqué facilement et qui offre une excellente efficacité de refroidissement. Ce dispositif semi-conducteur est pourvu : d'une paire de cartes isolantes (17, 19) sur lesquelles des cartes de circuit en cuivre (32, 34) sont fixées respectivement sur une surface de substrats céramiques (30, 33) et des plaques de cuivre (31, 35) sont fixées respectivement sur l'autre surface des substrats céramiques (30, 33) ; d'un boîtier en résine en forme de plaque (15) dans lequel une broche de signal (22) et des électrodes en plomb (23, 24) sont préalablement moulées par insertion ; d'une puce IGBT (11) et d'une puce FWD (13). Le boîtier de résine (15) est pourvu d'une partie ouverture (21) qui le traverse d'une surface avant (15A) à une surface arrière (15B), la puce IGBT (11) et la puce FWD (13) étant disposées côte à côte dans cette partie ouverture (21). La puce IGBT (11), la puce FWD (13) et les cartes de circuit en cuivre (32, 34) des cartes isolantes (17, 19) sont fixées entre elles par de la soudure de telle sorte que la puce IGBT (11), la puce FWD (13) et le boîtier de résine (15) sont pris en sandwich entre la paire de cartes isolantes (17, 19), les plaques de cuivre (31, 35) des cartes isolantes (17, 19) étant exposées.
(JA)
 製造が容易で優れた冷却性能を備える半導体装置を提供すること。 セラミック基板30,33の一面に銅回路基板32,34が接合され、他面に銅板31,35が接合された一対の絶縁基板17,19と、予め信号ピン22及びリード電極23,24がインサート成形された板状の樹脂ケース15と、IGBTチップ11及びFWDチップ13とを備え、樹脂ケース15が表面15A及び裏面15Bを貫通する開口部21を備え、この開口部21にIGBTチップ11及びFWDチップ13を並べて配置し、絶縁基板17,19の銅板31,34が露出するように、一対の絶縁基板17,19によりIGBTチップ11、FWDチップ13及び樹脂ケース15を挟み込んだ状態で、当該IGBTチップ11、FWDチップ13と、絶縁基板17,19の銅回路基板32,34とがハンダ接合された。
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