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出願の表示

1. WO2013001973 - 多層セラミック基板およびその製造方法ならびに電子部品モジュール

公開番号 WO/2013/001973
公開日 03.01.2013
国際出願番号 PCT/JP2012/064027
国際出願日 31.05.2012
IPC
H05K 3/46 2006.01
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
46多重層回路の製造
CPC
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2924/15174
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
15Details of package parts other than the semiconductor or other solid state devices to be connected
151Die mounting substrate
1517Multilayer substrate
15172Fan-out arrangement of the internal vias
15174in different layers of the multilayer substrate
H01L 2924/19105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
191Disposition
19101of discrete passive components
19105in a side-by-side arrangement on a common die mounting substrate
H05K 1/113
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
111Pads for surface mounting, e.g. lay-out
112directly combined with via connections
113Via provided in pad; Pad over filled via
H05K 3/246
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
22Secondary treatment of printed circuits
24Reinforcing the conductive pattern
245Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
246Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating
H05K 3/4007
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
40Forming printed elements for providing electric connections to or between printed circuits
4007Surface contacts, e.g. bumps
出願人
  • 株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP]/[JP] (AllExceptUS)
  • 福田 寛 FUKUDA, Yutaka [JP]/[JP] (UsOnly)
  • 足立 登志郎 ADACHI, Toshiro [JP]/[JP] (UsOnly)
  • 矢吹 裕昌 YABUKI, Hiromasa [JP]/[JP] (UsOnly)
  • 田中 佑亨 TANAKA, Hiromichi [JP]/[JP] (UsOnly)
発明者
  • 福田 寛 FUKUDA, Yutaka
  • 足立 登志郎 ADACHI, Toshiro
  • 矢吹 裕昌 YABUKI, Hiromasa
  • 田中 佑亨 TANAKA, Hiromichi
代理人
  • 小柴 雅昭 KOSHIBA, Masaaki
優先権情報
2011-14376529.06.2011JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) MULTILAYER CERAMIC SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND ELECTRONIC COMPONENT MODULE
(FR) SUBSTRAT CÉRAMIQUE MULTICOUCHE AINSI QUE PROCÉDÉ DE FABRICATION DE CELUI-CI, ET MODULE DE COMPOSANTS ÉLECTRONIQUES
(JA) 多層セラミック基板およびその製造方法ならびに電子部品モジュール
要約
(EN)
In order to improve bonding strength of a surface electrode on a multilayer ceramic substrate, an oxide, such as alumina, has been added to a conducting paste for forming the surface electrode, and reacted with a glass component in a ceramic material, while performing firing. There has been an issue of having infiltration of the glass component disturbed and having sintering of the surface electrode not sufficiently proceed in a surface electrode region in contact with a via conductor. In order to solve the issue, a surface layer via conductor (16) connected to a surface electrode (14) is formed such that the surface layer via conductor penetrates the surface electrode (14), and that one end portion of the surface layer via conductor is exposed from the surface electrode (14). Preferably, a plating film (15) or the like is formed on the surface electrode (14) and on the one end portion of the surface layer via conductor (16).
(FR)
L'invention a pour objectif d'ajouter un oxyde tel qu'une alumine, ou similaire, à une pâte conductrice pour formation d'électrode de surface, afin d'augmenter la résistance de liaison d'une électrode de surface sur un substrat céramique multicouche; d'effectuer une réaction avec un composant verre contenu dans un corps d'élément céramique, en cours de cuisson, mais d'empêcher l'infiltration de l'électrode de surface dans le composant verre au niveau d'une région en contact avec un conducteur d'interconnexion; et d'interrompre convenablement le frittage de l'électrode de surface. Afin d'atteindre cet objectif, le conducteur d'interconnexion de surface (16) connecté à l'électrode de surface (14), traverse cette dernière, et une de ses parties extrémité est formée de manière à être exposée hors de l'électrode de surface (14). De préférence, un film de placage (15), ou similaire, est formé sur l'électrode de surface (14) et sur cette partie extrémité du conducteur d'interconnexion de surface (16).
(JA)
 多層セラミック基板における表面電極の接合強度を高めるため、表面電極形成のための導電性ペーストにアルミナなどの酸化物を添加しておき、焼成中において、セラミック素体中のガラス成分と反応させることが行なわれるが、表面電極の、ビア導体に接する領域では、ガラス成分の浸透が阻害され、表面電極の焼結が十分に進まない、という課題がある。 この課題を解決するため、表面電極(14)に接続される表層ビア導体(16)を、表面電極(14)を貫通して、その一方端部が表面電極(14)から露出するように形成する。好ましくは、表面電極(14)上および表層ビア導体(16)の一方端部上に、めっき膜(15)などが形成される。
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