処理中

しばらくお待ちください...

設定

設定

出願の表示

1. WO2012141003 - 半導体装置およびその製造方法

公開番号 WO/2012/141003
公開日 18.10.2012
国際出願番号 PCT/JP2012/057867
国際出願日 27.03.2012
IPC
H01L 27/146 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
271つの共通基板内または上に形成された複数の半導体構成部品または他の固体構成部品からなる装置
14赤外線,可視光,短波長の電磁波または粒子線輻射に感応する半導体構成部品で,これらの輻射線エネルギーを電気的エネルギーに変換するかこれらの輻射線によって電気的エネルギーを制御するかのどちらかに特に適用されるもの
144輻射線によって制御される装置
146固体撮像装置構造
H01L 21/768 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
701つの共通基板内または上に形成された複数の固体構成部品または集積回路からなる装置またはその特定部品の製造または処理;集積回路装置またはその特定部品の製造
71グループH01L21/70で限定された装置の特定部品の製造
768装置内の別個の構成部品間に電流を流すため使用する相互接続を適用するもの
H01L 23/522 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
52動作中の装置内の1つの構成部品から他の構成部品へ電流を導く装置
522半導体本体上に分離できないように形成された導電層及び絶縁層の多層構造からなる外部の相互接続を含むもの
CPC
H01L 21/31056
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
31051Planarisation of the insulating layers
31053involving a dielectric removal step
31055the removal being a chemical etching step, e.g. dry etching
31056the removal being a selective chemical etching step, e.g. selective dry etching through a mask
H01L 21/32139
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
321After treatment
3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
32139using masks
H01L 21/76819
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76819Smoothing of the dielectric
H01L 27/14609
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144Devices controlled by radiation
146Imager structures
14601Structural or functional details thereof
14609Pixel-elements with integrated switching, control, storage or amplification elements
H01L 27/14621
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144Devices controlled by radiation
146Imager structures
14601Structural or functional details thereof
1462Coatings
14621Colour filter arrangements
H01L 27/14685
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144Devices controlled by radiation
146Imager structures
14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
14685Process for coatings or optical elements
出願人
  • ルネサスエレクトロニクス株式会社 RENESAS ELECTRONICS CORPORATION [JP]/[JP] (AllExceptUS)
  • 飯塚 康治 IIZUKA, Koji [JP]/[JP] (UsOnly)
発明者
  • 飯塚 康治 IIZUKA, Koji
代理人
  • 特許業務法人深見特許事務所 Fukami Patent Office, p.c.
優先権情報
2011-08905513.04.2011JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEURS ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置およびその製造方法
要約
(EN)
In this method for manufacturing a semiconductor device having an optical conversion element (PD), which has the topmost surface thereof planarized without making a step complicated, and improved optical characteristics, such as suppressed color unevenness, a topmost layer metal layer (AL3) is formed in both the effective chip region (AA) having the photoelectric conversion element (PD) formed therein, and the effective chip outside region (NAA), said effective chip region and effective chip outside region being on the main surface of a semiconductor substrate (SUB). The topmost layer metal layer (AL3) in the effective chip region (AA) is patterned, and the topmost layer metal layer (AL3) in the whole effective chip outside region (NAA) is removed. An interlayer insulating layer (II4) is formed in both the effective chip region (AA) and the effective chip outside region (NAA) such that the patterned topmost layer metal layer (AL3) in the effective chip region (AA) is covered. After removing a part of the upper surface of the interlayer insulating layer (II4) by selective etching, said part being positioned directly above the topmost layer metal layer (AL3) that has been patterned in the effective chip region (AA), the upper surface of the interlayer insulating layer (II4) is planarized.
(FR)
Dans ce procédé de fabrication d'un dispositif à semi-conducteurs ayant un élément de conversion optique (PD), dont la surface la plus haute est planarisée sans rendre une étape compliquée, et des caractéristiques optiques améliorées, telles qu'une irrégularité de couleur diminuée, une couche métallique (AL3) de couche la plus haute est formée à la fois dans la région de puce efficace (AA) ayant l'élément de conversion photoélectrique (PD) formé dans celle-ci, et dans la région hors puce efficace (NAA), ladite région de puce efficace et ladite région hors puce efficace étant sur la surface principale d'un substrat semi-conducteur (SUB). La couche métallique (AL3) de couche la plus haute dans la région de puce efficace (AA) est à motifs, et la couche métallique (AL3) de couche la plus haute dans la région hors puce efficace totale (NAA) est retirée. Une couche isolante intercouches (II4) est formée à la fois dans la région de puce efficace (AA) et dans la région hors puce efficace (NAA) de telle sorte que la couche (AL3) de couche métallique la plus haute à motifs dans la région de puce efficace (AA) est recouverte. Après retrait d'une partie de la surface supérieure de la couche isolante intercouches (II4) par gravure sélective, ladite partie étant positionnée directement au-dessus de la couche métallique (AL3) de couche la plus haute qui a été dotée de motifs dans la région de puce efficace (AA), la surface supérieure de la couche isolante intercouches (II4) est planarisée.
(JA)
 工程を煩雑にすることなく最上面が平坦化され、かつ色ムラを抑制するなど光学特性を向上することが可能な光学変換素子(PD)を有する半導体装置の製造方法は、半導体基板(SUB)の主表面の、光電変換素子(PD)が形成された有効チップ領域(AA)と、有効チップ外領域(NAA)との双方において最上層金属層(AL3)が形成される。有効チップ領域(AA)内の最上層金属層(AL3)がパターニングされ、かつ有効チップ外領域(NAA)全体の最上層金属層(AL3)が除去される。有効チップ領域(AA)においてパターニングされた最上層金属層(AL3)を覆うように有効チップ領域(AA)と有効チップ外領域(NAA)との双方に層間絶縁層(II4)が形成される。有効チップ領域(AA)内においてパターニングされた最上層金属層(AL3)の真上に位置する層間絶縁層(II4)の上面の一部が選択的にエッチングされることにより除去された上で、層間絶縁層(II4)の上面が平坦化される。
他の公開
国際事務局に記録されている最新の書誌情報