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1. WO2011077886 - 配線用電子部品及びその製造方法

公開番号 WO/2011/077886
公開日 30.06.2011
国際出願番号 PCT/JP2010/070920
国際出願日 24.11.2010
予備審査請求日 04.02.2011
IPC
H01L 23/12 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
12マウント,例.分離できない絶縁基板
H05K 1/02 2006.01
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
1印刷回路
02細部
CPC
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/45144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
45144Gold (Au) as principal constituent
H01L 2224/48227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
H01L 2224/73204
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73201on the same surface
73203Bump and layer connectors
73204the bump connector being embedded into the layer connector
H01L 2224/73265
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73251on different surfaces
73265Layer and wire connectors
出願人
  • 国立大学法人九州工業大学 KYUSHU INSTITUTE OF TECHNOLOGY [JP]/[JP] (AllExceptUS)
  • 積水化学工業株式会社 SEKISUI CHEMICAL CO.,LTD. [JP]/[JP] (AllExceptUS)
  • 石原 政道 ISHIHARA, Masamichi [JP]/[JP] (UsOnly)
  • 榎本 實 ENOMOTO, Minoru [JP]/[JP] (UsOnly)
  • 野村 茂 NOMURA, Shigeru [JP]/[JP] (UsOnly)
発明者
  • 石原 政道 ISHIHARA, Masamichi
  • 榎本 實 ENOMOTO, Minoru
  • 野村 茂 NOMURA, Shigeru
代理人
  • 大川 譲 OHKAWA, Yuzuru
優先権情報
2009-29023522.12.2009JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) INTERCONNECT-USE ELECTRONIC COMPONENT AND METHOD FOR PRODUCING SAME
(FR) COMPOSANT ÉLECTRONIQUE À USAGE D'INTERCONNEXION ET PROCÉDÉ DE PRODUCTION ASSOCIÉ
(JA) 配線用電子部品及びその製造方法
要約
(EN)
Provided is a method for producing an interconnect-use electronic component, wherein vertical interconnects and redistribution interconnects which are formed in an additional step in producing a dual face package (DFP) or a wafer level chip size package (WLCSP) are integrated as components, the production steps involved in the above being further simplified to reduce costs. The interconnect-use electronic component is embedded into an electronic device package in which a circuit element comprising a semiconductor chip is disposed and connected to an external electrode via vertical and horizontal interconnects. The electronic component for interconnect comprises: an interconnect substrate having a horizontal interconnect and a vertical interconnect which is connected to the horizontal interconnect and extends vertically therefrom; and a support substrate to which the interconnect substrate having the horizontal and vertical interconnects is bonded with an adhesive which is removable with water.
(FR)
La présente invention a trait à un procédé de production d'un composant électronique à usage d'interconnexion permettant d'intégrer en tant que composants des interconnexions verticales et des interconnexions de redistribution qui sont formées lors d'une étape supplémentaire dans la production d'un boîtier de circuit intégré à double face (DFP) ou d'une encapsulation sur tranches (WLCSP), les étapes de production impliquées dans ledit procédé étant davantage simplifiées afin de réduire les coûts. Le composant électronique à usage d'interconnexion est intégré dans un boîtier de dispositif électronique dans lequel un élément de circuit comprenant une puce de semi-conducteur est disposé et connecté à une électrode extérieure par l'intermédiaire d'interconnexions verticales et horizontales. Le composant électronique pour l'interconnexion comprend : un substrat d'interconnexion doté d'une interconnexion horizontale et d'une interconnexion verticale qui est connectée à l'interconnexion horizontale et qui s'étend verticalement à partir de celle-ci ; et un substrat de support auquel le substrat d'interconnexion doté des interconnexions horizontale et verticale est collé au moyen d'un adhésif qui peut être retiré avec de l'eau.
(JA)
 本発明は、両面電極パッケージDFPやウエハレベルチップサイズパッケージWLCSPの追加工程として構造形成される垂直配線や再配線を部品として集約させ、かつ、その際に、製造工程をより簡素化してコスト低減を実現する。配線用電子部品は、半導体チップを含む回路素子を配置し、該回路素子から垂直配線及び水平配線を介して外部電極に接続される電子デバイスパッケージに組み込んで用いられる。この配線用電子部品は、水平配線、及び該水平配線に接続されてそこから垂直方向に伸びる垂直配線を備えた配線基板と、水平配線及び垂直配線を備えている配線基板が水で剥離可能の接着剤を用いて接着されている支持板とから構成される。
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