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1. WO2011077536 - 半導体装置およびその製造方法

公開番号 WO/2011/077536
公開日 30.06.2011
国際出願番号 PCT/JP2009/071492
国際出願日 24.12.2009
IPC
H01L 21/8238 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
701つの共通基板内または上に形成された複数の固体構成部品または集積回路からなる装置またはその特定部品の製造または処理;集積回路装置またはその特定部品の製造
771つの共通基板内または上に形成される複数の固体構成部品または集積回路からなる装置の製造または処理
78複数の別個の装置に基板を分割することによるもの
82それぞれが複数の構成部品からなる装置,例.集積回路の製造
822基板がシリコン技術を用いる半導体であるもの
8232電界効果技術
8234MIS技術
8238相補型電界効果トランジスタ,例.CMOS
H01L 27/092 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
271つの共通基板内または上に形成された複数の半導体構成部品または他の固体構成部品からなる装置
02整流,発振,増幅またはスイッチングに特に適用される半導体構成部品を含むものであり,少なくとも1つの電位障壁または表面障壁を有するもの;少なくとも1つの電位障壁または表面障壁を有する集積化された受動回路素子を含むもの
04基板が半導体本体であるもの
081種類の半導体構成部品だけを含むもの
085電界効果構成部品のみを含むもの
088構成部品が絶縁ゲートを有する電界効果トランジスタであるもの
092相補型MIS電界効果トランジスタ
H01L 29/78 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
29整流,増幅,発振またはスイッチングに特に適用される半導体装置であり,少なくとも1つの電位障壁または表面障壁を有するもの;少なくとも1つの電位障壁または表面障壁,例.PN接合空乏層またはキャリア集中層,を有するコンデンサーまたは抵抗器;半導体本体または電極の細部
66半導体装置の型
68整流,増幅またはスイッチされる電流を流さない電極に電流のみまたは電位のみを与えることにより制御できるもの
76ユニポーラ装置
772電界効果トランジスタ
78絶縁ゲートによって生じる電界効果を有するもの
CPC
H01L 21/28194
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
28008Making conductor-insulator-semiconductor electrodes
28017the insulator being formed after the semiconductor body, the semiconductor being silicon
28158Making the insulator
28167on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
28194by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
H01L 21/823842
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823828with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
823842gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
H01L 21/823857
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823857with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
H01L 29/4966
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
4966the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
H01L 29/513
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
51Insulating materials associated therewith
511with a compositional variation, e.g. multilayer structures
513the variation being perpendicular to the channel plane
H01L 29/518
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
51Insulating materials associated therewith
518the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
出願人
  • ルネサスエレクトロニクス株式会社 Renesas Electronics Corporation [JP]/[JP] (AllExceptUS)
  • 由上 二郎 YUGAMI, Jiro [JP]/[JP] (UsOnly)
発明者
  • 由上 二郎 YUGAMI, Jiro
代理人
  • 筒井 大和 TSUTSUI, Yamato
優先権情報
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCESSUS DE PRODUCTION
(JA) 半導体装置およびその製造方法
要約
(EN)
A p-type MIS transistor (Qp) arranged in a pMIS region (Rp) in a silicon substrate (1) has a pMIS gate electrode (GEp) that is formed through a pMIS gate insulating film (GIp) comprising a first insulating film (z1) and a first highly dielectric film (hk1), and an n-type MIS transistor (Qn) arranged in an nMIS region (Rn) has an nMIS gate electrode (GEn) that is formed through an nMIS gate insulating film (GIn) comprising the first insulating film (z1) and a second highly dielectric film (hk2). The first highly dielectric film (hk1) comprises an insulating film that is mainly composed of hafnium and oxygen and contains aluminum, titanium or tantalum. The second highly dielectric film (hk2) comprises an insulating film that is mainly composed of hafnium, silicon and oxygen and contains an element belonging to Group Ia, IIa or IIIa.
(FR)
Dans la présente invention, un transistor MIS de type p (Qp) disposé dans une zone pMIS (Rp) dans un substrat de silicium (1) comporte une électrode de gâchette pMIS (GEp) qui est formée à travers une pellicule d'isolation de gâchette pMIS (GIp) comprenant une première pellicule isolante (z1) et une première pellicule hautement diélectrique (hk1), et un transistor MIS de type n (Qn) disposé dans une zone nMIS (Rn) comporte une électrode de gâchette nMIS (GEn) qui est formée à travers une pellicule d'isolation de gâchette nMIS (GIn) comprenant la première pellicule isolante (z1) et une seconde pellicule hautement diélectrique (hk2). La première pellicule hautement diélectrique (hk1) comprend une pellicule isolante qui est principalement composée d'hafnium et d'oxygène et contient de l'aluminium, du titane ou du tantale. La seconde pellicule hautement diélectrique (hk2) comprend une pellicule isolante qui est principalement composée d'hafnium, de silicium et d'oxygène et contient un élément appartenant au groupe Ia, IIa ou IIIa.
(JA)
 シリコン基板1のpMIS領域Rpに配置されたp型MISトランジスタQpは、第1絶縁膜z1および第1高誘電体膜hk1からなるpMIS用ゲート絶縁膜GIpを介して形成されたpMIS用ゲート電極GEpを有し、nMIS領域Rnに配置されたn型MISトランジスタQnは、第1絶縁膜z1および第2高誘電体膜hk2からなるnMIS用ゲート絶縁膜GInを介して形成されたnMIS用ゲート電極GEnを有している。第1高誘電体膜hk1は、ハフニウムおよび酸素を主体とし、アルミニウム、チタンまたはタンタルを含む絶縁膜からなる。また、第2高誘電体膜hk2は、ハフニウム、シリコンおよび酸素を主体とし、Ia族、IIa族またはIIIa族のいずれかの元素を含む絶縁膜からなる。
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