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1. WO2010067610 - 半導体モジュール、半導体モジュールの製造方法および携帯機器

公開番号 WO/2010/067610
公開日 17.06.2010
国際出願番号 PCT/JP2009/006765
国際出願日 10.12.2009
IPC
H01L 21/60 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
50サブグループH01L21/06~H01L21/326の一つに分類されない方法または装置を用いる半導体装置の組立
60動作中の装置にまたは装置から電流を流すためのリードまたは他の導電部材の取り付け
H01L 23/12 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
12マウント,例.分離できない絶縁基板
CPC
H01L 21/563
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
H01L 2224/02319
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0231Manufacturing methods of the redistribution layers
02319by using a preform
H01L 2224/02333
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0233Structure of the redistribution layers
02333being a bump
H01L 2224/02379
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02379Fan-out arrangement
H01L 2224/02381
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02381Side view
H01L 2224/0239
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0239Material of the redistribution layers
出願人
  • 三洋電機株式会社 SANYO ELECTRIC CO., LTD. [JP]/[JP] (AllExceptUS)
  • 中里真弓 NAKASATO, Mayumi [JP]/[JP] (UsOnly)
  • 伊藤克実 ITO, Katsumi [JP]/[JP] (UsOnly)
  • 臼井良輔 USUI, Ryosuke [JP]/[JP] (UsOnly)
  • 五十嵐優助 IGARASHI, Yusuke [JP]/[JP] (UsOnly)
発明者
  • 中里真弓 NAKASATO, Mayumi
  • 伊藤克実 ITO, Katsumi
  • 臼井良輔 USUI, Ryosuke
  • 五十嵐優助 IGARASHI, Yusuke
代理人
  • 森下賢樹 MORISHITA, Sakaki
優先権情報
2008-31496010.12.2008JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND PORTABLE APPARATUS
(FR) MODULE À SEMI-CONDUCTEUR, PROCÉDÉ DE FABRICATION DE MODULE À SEMI-CONDUCTEUR ET APPAREIL PORTABLE
(JA) 半導体モジュール、半導体モジュールの製造方法および携帯機器
要約
(EN)
A semiconductor module (10) is provided with an element mounting substrate (20) and a semiconductor element (30).  The semiconductor element (30) is connected to the element mounting substrate (20) by flip-chip connection, and element electrodes (32) provided on the semiconductor element (30) and substrate electrodes (24a) provided on the element mounting substrate (20) are connected using a solder (70).  In the cross-section along the line connecting the adjacent substrate electrodes (24a), the width (L1) of the substrate electrode (24a) is smaller than the width (L2) of an element electrode (32) that corresponds to the substrate electrode (24a).
(FR)
L'invention porte sur un module à semi-conducteur (10) qui comprend un substrat de montage d'élément (20) et un élément à semi-conducteur (30). L'élément à semi-conducteur (30) est connecté au substrat de montage d'élément (20) par une connexion puce retournée, et des électrodes d'élément (32) formées sur l'élément à semi-conducteur (30) et des électrodes de substrat (24a) formées sur le substrat de montage d'élément (20) sont connectées à l'aide d'une soudure (70). Dans la section transversale suivant la ligne reliant les électrodes de substrat adjacentes (24a), la largeur (L1) de l'électrode de substrat (24a) est inférieure à la largeur (L2) d'une électrode d'élément (32) qui correspond à l'électrode de substrat (24a).
(JA)
 半導体モジュール10は、素子搭載用基板20および半導体素子30を備える。半導体素子30は素子搭載用基板20にフリップチップ接続されており、半導体素子30に設けられた素子電極32と素子搭載用基板20に設けられた基板電極24aとがはんだ70により接続されている。隣接する基板電極24aを結ぶ線に沿った断面において、基板電極24aの幅L1は、基板電極24aに対応する素子電極32の幅L2に比べて狭くなっている。
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