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1. WO2010061552 - 電子部品パッケージおよび電子部品パッケージの製造方法

公開番号 WO/2010/061552
公開日 03.06.2010
国際出願番号 PCT/JP2009/006232
国際出願日 19.11.2009
IPC
H01L 21/60 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
50サブグループH01L21/06~H01L21/326の一つに分類されない方法または装置を用いる半導体装置の組立
60動作中の装置にまたは装置から電流を流すためのリードまたは他の導電部材の取り付け
H01L 23/12 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
12マウント,例.分離できない絶縁基板
CPC
H01L 2221/68331
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2221Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
683for supporting or gripping
68304using temporarily an auxiliary support
68327used during dicing or grinding
68331of passive members, e.g. die mounting substrate
H01L 2221/68336
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2221Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
683for supporting or gripping
68304using temporarily an auxiliary support
68327used during dicing or grinding
68336involving stretching of the auxiliary support post dicing
H01L 2224/1134
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
11Manufacturing methods
113by local deposition of the material of the bump connector
1133in solid form
1134Stud bumping, i.e. using a wire-bonding apparatus
H01L 2224/131
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
13099Material
131with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
H01L 2224/13109
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
13099Material
131with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
13101the principal constituent melting at a temperature of less than 400°C
13109Indium [In] as principal constituent
H01L 2224/16
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
出願人
  • 住友ベークライト株式会社 SUMITOMO BAKELITE CO., LTD. [JP]/[JP] (AllExceptUS)
  • 中馬敏秋 CHUMA, Toshiaki [JP]/[JP] (UsOnly)
  • 近藤正芳 KONDO, Masayoshi [JP]/[JP] (UsOnly)
  • 田中哲 TANAKA, Satoshi [JP]/[JP] (UsOnly)
  • 兼政賢一 KANEMASA, Kenichi [JP]/[JP] (UsOnly)
発明者
  • 中馬敏秋 CHUMA, Toshiaki
  • 近藤正芳 KONDO, Masayoshi
  • 田中哲 TANAKA, Satoshi
  • 兼政賢一 KANEMASA, Kenichi
代理人
  • 速水進治 HAYAMI, Shinji
優先権情報
2008-30011325.11.2008JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC COMPONENT PACKAGE MANUFACTURING METHOD
(FR) BOÎTIER DE COMPOSANT ÉLECTRONIQUE ET PROCÉDÉ DE FABRICATION DE BOÎTIER DE COMPOSANT ÉLECTRONIQUE
(JA) 電子部品パッケージおよび電子部品パッケージの製造方法
要約
(EN)
The electronic component package (100) comprises a circuit board (10), an electronic component (20), and an adhesive layer (30). The circuit board (10) has electrically-conductive conductor posts (16) which are buried in a substrate (12), and solder layers (18) which are provided at the front ends (13) of the conductor posts (16) while exposed from a surface (121) of the substrate (12). Electrode pads (24), each carrying a metal layer (22), are provided on the primary surface (26) of the electronic component (20). The adhesive layer (30) contains a flux active compound and bonds the surface (121) of the substrate (12) and the primary surface (26) of the electronic component (20). Then the metal layer (22) and the solder layer (18) are metal bonded.
(FR)
L'invention porte sur un boîtier de composant électronique (100) qui comprend une carte de circuit imprimé (10), un composant électronique (20) et une couche adhésive (30). La carte de circuit imprimé (10) comprend des tiges électriquement conductrices (16) qui sont enfouies dans un substrat (12), et des couches de soudure (18) qui sont formées au niveau des extrémités avant (13) des tiges conductrices (16) tout en étant exposées par rapport à une surface (121) du substrat (12). Des plots d'électrode (24), portant chacun une couche métallique (22), sont formés sur la surface primaire (26) du composant électronique (20). La couche adhésive (30) contient un composé actif de flux et lie la surface (121) du substrat (12) et la surface primaire (26) du composant électronique (20). La couche métallique (22) et la couche de soudure (18) sont ensuite liées métalliquement.
(JA)
 電子部品パッケージ(100)は、回路基板(10)と電子部品(20)と接着層(30)とを含む。回路基板(10)は、基材(12)に埋設された導電性の導体ポスト(16)と、導体ポスト(16)の先端部(13)に基材(12)の表面(121)より露出して設けられたハンダ層(18)とを備えている。電子部品(20)の主面(26)には、金属層(22)が搭載された電極パッド(24)が設けられている。接着層(30)は、フラックス活性化合物を含有し、基材(12)の表面(121)と電子部品(20)の主面(26)とを接合する。そして、金属層(22)とハンダ層(18)とは金属接合されている。
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