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1. WO2009072544 - 電極構造及びその製造方法、回路基板、半導体モジュール

公開番号 WO/2009/072544
公開日 11.06.2009
国際出願番号 PCT/JP2008/072019
国際出願日 04.12.2008
IPC
H01L 23/12 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
23半導体または他の固体装置の細部
12マウント,例.分離できない絶縁基板
H01L 21/60 2006.01
H電気
01基本的電気素子
L半導体装置,他に属さない電気的固体装置
21半導体装置または固体装置またはそれらの部品の製造または処理に特に適用される方法または装置
02半導体装置またはその部品の製造または処理
04少なくとも一つの電位障壁または表面障壁,例.PN接合,空乏層,キャリア集中層,を有する装置
50サブグループH01L21/06~H01L21/326の一つに分類されない方法または装置を用いる半導体装置の組立
60動作中の装置にまたは装置から電流を流すためのリードまたは他の導電部材の取り付け
CPC
H01L 2224/05082
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05075Plural internal layers
0508being stacked
05082Two-layer arrangements
H01L 2224/05147
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05147Copper [Cu] as principal constituent
H01L 2224/05155
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05155Nickel [Ni] as principal constituent
H01L 2224/05164
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05163the principal constituent melting at a temperature of greater than 1550°C
05164Palladium [Pd] as principal constituent
H01L 2224/05644
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05638the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05644Gold [Au] as principal constituent
H01L 2224/45015
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
4501Shape
45012Cross-sectional shape
45015being circular
出願人
  • 日立金属株式会社 HITACHI METALS, LTD. [JP]/[JP] (AllExceptUS)
  • 安藤 節夫 ANDOH, Setsuo [JP]/[JP] (UsOnly)
  • 谷口 文丈 TANIGUCHI, Fumitake [JP]/[JP] (UsOnly)
発明者
  • 安藤 節夫 ANDOH, Setsuo
  • 谷口 文丈 TANIGUCHI, Fumitake
代理人
  • 堀 城之 HORI, Shiroyuki
優先権情報
2007-31353504.12.2007JP
公開言語 (言語コード) 日本語 (JA)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) ELECTRODE STRUCTURE, METHOD FOR MANUFACTURING THE ELECTRODE STRUCTURE, AND CIRCUIT BOARD AND SEMICONDUCTOR MODULE
(FR) STRUCTURE D'ÉLECTRODE, PROCÉDÉ DE FABRICATION ASSOCIÉ, CARTE DE CIRCUIT IMPRIMÉ ET MODULE SEMI-CONDUCTEUR
(JA) 電極構造及びその製造方法、回路基板、半導体モジュール
要約
(EN)
Disclosed is a highly reliable semiconductor module which has sufficient bonding strength at an electrically bonding section. Specifically, in the semiconductor module (10), a semiconductor chip (11) is mounted on a circuit board (20). In the circuit board (20), a metal circuit board (22) is formed on an insulating ceramic substrate (21) and the semiconductor chip (11) is mounted. The semiconductor chip (11) and the metal circuit board (22) are connected by a bonding wire (23) made of aluminum (Al). On the connecting section where the metal circuit board (22) and the bonding wire (23) are connected to each other, a coat layer (24) is formed for improving such bonding. The coat layer (24) is composed of a nickel (Ni) layer (241), a palladium (Pd) layer (242) wherein phosphorus (P) is distributed and a gold (Au) layer (243) sequentially from the lower side, as shown in Fig. 1. Phosphorus (P) is added in the P-distributed Pd layer (242), and specifically, the P concentration is higher on the side of the Au layer (243) than that on the side of the Ni layer (241).
(FR)
La présente invention concerne un module semi-conducteur très fiable qui présente un pouvoir adhésif suffisant dans une section de liaison électrique. Particulièrement, dans le module semi-conducteur (10), une puce semi-conductrice (11) est montée sur une carte de circuit imprimé (20). Dans la carte de circuit imprimé (20), une carte de circuit imprimé métallique (22) est formée sur un substrat en céramique isolant (21) et la puce semi-conductrice (11) est montée. La puce semi-conductrice (11) et la carte de circuit imprimé métallique (22) sont connectées par un fil de connexion (23) fait d'aluminium (Al). Sur la section de connexion où la carte de circuit imprimé métallique (22) et le fil de connexion (23) sont connectés l'un à l'autre, une couche de revêtement (24) est formée pour optimiser une telle liaison. La couche de revêtement (24) se compose d'une couche de nickel (Ni) (241), d'une couche de palladium (Pd) (242), du phosphore (P) et une couche d'or (Au) (243) étant distribués séquentiellement à partir du côté inférieur, comme indiqué sur la figure 1. Du phosphore (P) est ajouté dans la couche de Pd à P distribué (242), et particulièrement, la concentration en P est plus élevée sur le côté de la couche d'Au (243) que sur le côté de la couche de Ni (241).
(JA)
 電気的接合部における充分な接合強度をもち、高い信頼性をもった半導体モジュールを得る。この半導体モジュール10においては、回路基板20上に半導体チップ11が搭載される。回路基板20においては、絶縁性のセラミックス基板21上に、金属回路板22が形成され、半導体チップ11が搭載される。半導体チップ11と金属回路板22とはアルミニウム(Al)製のボンディングワイヤ23で接続される。金属回路板22とボンディングワイヤ23との接続部分には、これらの間の接合を良好にするための被覆層24が設けられている。被覆層24は、図1における拡大図に示されるように、下側からニッケル(Ni)層241、リン(P)分布パラジウム(Pd)層242、金(Au)層243で構成される。P分布Pd層242にはリン(P)が添加されており、特にこのP濃度は、Ni層241側よりも、Au層243側で高くなっている。
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