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1. WO2004019667 - 二層積層膜を用いた電極パッド上へのバンプ形成方法

公開番号 WO/2004/019667
公開日 04.03.2004
国際出願番号 PCT/JP2003/010569
国際出願日 21.08.2003
IPC
H05K 3/28 2006.1
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
22印刷回路の2次的処理
28非金属質の保護被覆を施すこと
H05K 3/34 2006.1
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
30電気部品,例.抵抗器,を印刷回路に取り付けること
32印刷回路に対する電気部品または電線の電気的接続
34ハンダ付けによるもの
CPC
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/0603
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
0601Structure
0603Bonding areas having different sizes, e.g. different heights or widths
H01L 2224/06102
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
061Disposition
06102the bonding areas being at different heights
H01L 2224/10126
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
1012Auxiliary members for bump connectors, e.g. spacers
10122being formed on the semiconductor or solid-state body to be connected
10125Reinforcing structures
10126Bump collar
H01L 2224/1131
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
11Manufacturing methods
113by local deposition of the material of the bump connector
1131in liquid form
H01L 2224/11334
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
11Manufacturing methods
113by local deposition of the material of the bump connector
1133in solid form
11334using preformed bumps
出願人
  • JSR CORPORATION [JP]/[JP] (AllExceptUS)
  • OHTA, Masaru [JP]/[JP] (UsOnly)
  • INOMATA, Katsumi [JP]/[JP] (UsOnly)
  • IWANAGA, Shinichiro [JP]/[JP] (UsOnly)
発明者
  • OHTA, Masaru
  • INOMATA, Katsumi
  • IWANAGA, Shinichiro
代理人
  • SUZUKI, Shunichiro
優先権情報
2002-24250922.08.2002JP
2003-2360231.01.2003JP
公開言語 (言語コード) 日本語 (ja)
出願言語 (言語コード) 日本語 (JA)
指定国 (国コード)
発明の名称
(EN) METHOD FOR FORMING BUMP ON ELECTRODE PAD WITH USE OF DOUBLE-LAYERED FILM
(FR) PROCEDE SERVANT A CREER UNE PROTUBERANCE SUR UNE PASTILLE D'ELECTRODE AU MOYEN D'UN FILM DOUBLE COUCHE
(JA) 二層積層膜を用いた電極パッド上へのバンプ形成方法
要約
(EN) A method for forming a bump on an electrode pad characterized in that at least the following steps (a)-(d) are conducted on a wiring substrate which is composed of a base and a plurality of electrode pads: (a) a step wherein a double-layered film composed of a lower layer made of an alkali-soluble, radiation-nonsensitive resin composition and an upper layer made of a negative, radiation-sensitive resin composition is formed on the wiring substrate, and then an aperture pattern is formed in a corresponding position of the electrode pad; (b) a step wherein a low-melting metal is introduced into the aperture pattern; (c) a step wherein the low-melting metal is reflowed by conducting a press or a heat treatment so as to from a bump, and (d) a step wherein the double-layered film is removed from the substrate. By using the double-layered film having different characteristics, the high-resolution property and the easy-release property become compatible.
(FR) Procédé servant à créer une protubérance sur une pastille d'électrode et consistant à exécuter, de façon caractéristique, les étapes suivantes (a) - (d) sur un substrat de câblage composé d'une pluralité de pastilles d'électrode : (a) dépôt sur le substrat de câblage d'un film double couche composé d'une couche inférieure constituée par une composition de résine soluble dans une base non photosensible et d'une couche supérieure constituée par une composition de résine négative photosensible, puis création d'un motif ajouré dans une position correspondante de la pastille d'électrode, (b) introduction d'un métal à point de fusion bas dans ce motif ajouré ; (c) reflux de ce métal à point de fusion bas au moyen d'une presse ou d'un traitement thermique de manière à obtenir une protubérance et (d) suppression du film double couche du substrat. Utilisation de ce film double couche pourvu de caractéristiques différentes rend compatibles les propriétés de résolution élevée et de détachement facile.
(JA) not available
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