処理中

しばらくお待ちください...

設定

設定

出願の表示

1. US20060034133 - Sense amplifier for semiconductor memory device

官庁 アメリカ合衆国
出願番号 10534049
出願日 06.05.2005
公開番号 20060034133
公開日 16.02.2006
特許番号 7200061
特許付与日 03.04.2007
公報種別 B2
IPC
G11C 7/02
G物理学
11情報記憶
C静的記憶
7デジタル記憶装置に情報を書き込みまたはデジタル記憶装置から情報を読み出す機構
02寄生信号を回避する手段をもつもの
G11C 5/06
G物理学
11情報記憶
C静的記憶
5G11C11/00に分類される記憶装置の細部
06記憶素子を電気的に相互結合する機構,例.ワイヤリング
G11C 7/06
G物理学
11情報記憶
C静的記憶
7デジタル記憶装置に情報を書き込みまたはデジタル記憶装置から情報を読み出す機構
06センス増幅器;関連回路
G11C 7/08
G物理学
11情報記憶
C静的記憶
7デジタル記憶装置に情報を書き込みまたはデジタル記憶装置から情報を読み出す機構
06センス増幅器;関連回路
08その制御
G11C 7/10
G物理学
11情報記憶
C静的記憶
7デジタル記憶装置に情報を書き込みまたはデジタル記憶装置から情報を読み出す機構
10入力/出力データ・インターフェイス装置,例.I/Oデータ制御回路,I/Oデータバッファ
G11C 7/12
G物理学
11情報記憶
C静的記憶
7デジタル記憶装置に情報を書き込みまたはデジタル記憶装置から情報を読み出す機構
12ビット線制御回路,例.ビット線用の,ドライバ,ブースター,プルアップ回路,プルダウン回路,プリチャージング回路,等化回路
CPC
G11C 7/062
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits, ; e.g. timing or triggering circuits
062Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
G11C 5/063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
G11C 7/065
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits, ; e.g. timing or triggering circuits
065Differential amplifiers of latching type
G11C 7/08
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits, ; e.g. timing or triggering circuits
08Control thereof
G11C 7/1078
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
G11C 7/1096
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
1096Write circuits, e.g. I/O line write drivers
出願人 Hitachi, Ltd.
Elpida Memory, Inc.
Hitachi ULSI Systems Co., Ltd.
発明者 Sekiguchi Tomonori
Miyatake Shinichi
Sakata Takeshi
Takemura Riichiro
Noda Hiromasa
Kajigaya Kazuhiko
優先権情報 JP02011659 08.11.2002 WO
発明の名称
(EN) Sense amplifier for semiconductor memory device
要約
(EN)

A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.