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1. EP1633175 - INTERLAYER INSULATING LAYER FOR PRINTED WIRING BOARD, PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING SAME

官庁 欧州特許庁(EPO)
出願番号 04788447
出願日 29.09.2004
公開番号 1633175
公開日 08.03.2006
公報種別 A4
IPC
H05K 3/46
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
46多重層回路の製造
H05K 3/00
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
H05K 3/04
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
02導電性物質が絶縁支持部材の表面に施されその後電流の伝導や遮へいのために使わない部分が表面から取り除かれるもの
04導電性物質が機械的に取り除かれるもの,例.パンチによるもの
H05K 3/10
H電気
05他に分類されない電気技術
K印刷回路;電気装置の箱体または構造的細部,電気部品の組立体の製造
3印刷回路を製造するための装置または方法
10導電性物質が希望する導電模様を形成するように絶縁支持部材に施されるもの
CPC
H01L 23/145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
14characterised by the material or its electrical properties
145Organic substrates, e.g. plastic
H01L 23/49822
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49822Multilayer substrates
H01L 23/49827
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
H01L 2224/0554
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
H01L 2224/05568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05568the whole external layer protruding from the surface
H01L 2224/05573
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05573Single external layer
出願人 IBIDEN CO LTD
発明者 ASAI MOTOO
NODA KOUTA
INAGAKI YASUSHI
指定国 (国コード)
優先権情報 2003336861 29.09.2003 JP
2004014672 29.09.2004 JP
2004194868 30.06.2004 JP
発明の名称
(DE) ZWISCHENSCHICHT-ISOLATIONSSCHICHT FÜR EINE LEITERPLATTE, LEITERPLATTE UND HERSTELLUNGSVERFAHREN DAFÜR
(EN) INTERLAYER INSULATING LAYER FOR PRINTED WIRING BOARD, PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING SAME
(FR) INTERCOUCHE D'ISOLATION POUR CARTE DE CONNEXIONS IMPRIMEE, CARTE DE CONNEXIONS IMPRIMEE ET PROCEDE DE FABRICATION ASSOCIE
要約
(EN)
A printed wiring board is provided which includes an interlayer dielectric layer formed on a substrate from a curable resin having flaky particles dispersed therein. The printed wiring board is excellent in cooling/heating cycle resistance and packaging reliability while maintaining a satisfactory heat resistance, electrical insulation, heat liberation, connection reliability and chemical stability. Also a method of producing a printed wiring board is proposed in which an imprint method using a mold having formed thereon convexities corresponding to wiring patterns and viaholes to be formed being buried in an interlayer dielectric layer is used to form the wiring patterns and viaholes by transcribing the concavities of the mold to the interlayer dielectric layer. The imprint method permits to form the wiring patterns and viaholes but assures an easy and accurate transcription without any optical transcription or complicated etching. Thus, a multilayer printed wiring board excellent in insulation reliability and interlayer connection and having fine wiring patterns formed therein can be mass-produced extremely easily and inexpensively.

(FR)
L'invention concerne une intercouche d'isolation pour des cartes de connexions imprimées, laquelle est formée sur un substrat et composée d'une résine pouvant être durcie dans laquelle sont dispersées des particules de type écaille. L'invention concerne également une carte de connexions imprimée grandement améliorée pour ce qui est de la résistance aux cycles de chaleur et la fiabilité d'assemblage sans que ne soient diminuées les qualités d'isolation électrique, de dissipation de la chaleur et de fiabilité de connexion ou de stabilité chimique. L'invention concerne encore un procédé de fabrication d'une carte de connexions imprimée qui permet de transférer facilement et avec précision un motif de connexions ou un trou de raccordement sur l'intercouche d'isolation, au moyen d'un procédé d'impression dans lequel un moule possédant une partie en saillie correspondant au motif de connexions est utilisé. Ce procédé ne nécessite pas de procédé de transfert optique ou de gravure compliquée pour former le motif de connexions ou le trou de raccordement. Grâce à ce procédé, une carte de connexions imprimée possédant un motif de connexions très fin, excellente pour ce qui est de la fiabilité d'isolation et la connexion intercouche, peut être produite en série à faible coût.