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出願の表示

1. CN1695249 - Semiconductor method

官庁 中華人民共和国
出願番号 02829837.3
出願日 08.11.2002
公開番号 1695249
公開日 09.11.2005
特許番号 100354971
特許付与日 12.12.2007
公報種別 C
IPC
G11C 7/06
G物理学
11情報記憶
C静的記憶
7デジタル記憶装置に情報を書き込みまたはデジタル記憶装置から情報を読み出す機構
06センス増幅器;関連回路
CPC
G11C 5/063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
出願人 Hitachi Ltd
株式会社日立制作所
尔必达存储器株式会社
日立超大规模集成电路系统株式会社
発明者 Kajigaya Kazuhiko
关口知纪
Miyatake Shinichi
宫武伸一
Noda Hiromasa
阪田健
Sakata Takeshi
竹村理一郎
Sekiguchi Tomonori
野田浩正
Takemura Riichiro
梶谷一彦
代理人 wang sibeng
中国国际贸易促进委员会专利商标事务所
発明の名称
(EN) Semiconductor method
(ZH) 半导体存储装置
要約
(EN)
A direct sense amplifier isolates an MOS transistor serving as a differential pair having a gate being connected with a bit line from an RLIO line by inserting an MOS transistor being controlled by a column select line arranged in the direction of the bit line between them and connects the source of the MOS transistor serving as a differential pair with a common source line arranged in the direction of the word line. Power consumption is reduced greatly at the time of read operation by activating the direct sense amplifier only at a select mat through the column select line and the common source line. Higher-rate reading operation is realized by isolating the parasitic capacitance of the MOS transistor serving as a differential pair from a local IO line thereby reducing the load capacity of the local IO line, and test after fabrication is facilitated by reducing the data pattern dependency of the load capacity of the local IO line during the reading operation.

(ZH)

本发明的直接读出放大器,在作为位线连接到栅极的差动对而动作的MOS晶体管和RLIO线之间,设置由在位线方向上布线的读出列选择线所控制的MOS晶体管而使其隔离,进而,把作为差动对而动作的MOS晶体管的源极连接到在字线方向上布线的共同源极线上。在读出动作时,通过利用读出列选择线和共同源极线仅在选择栅网上激活直接读出放大器,而大幅度地减少读出动作时的消耗电力。而且,从局部IO线隔离作为差动对动作的MOS晶体管的寄生电容,减少局部IO线的负载能力,实现读出速度的高速化。另外,降低读出动作中的局部IO线的负载能力的数据模式依赖性,使制造后的试验容易化。