Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

Aller à Demande

1. WO2022068767 - MÉMOIRE TRIDIMENSIONNELLE ET SON PROCÉDÉ DE FABRICATION

Numéro de publication WO/2022/068767
Date de publication 07.04.2022
N° de la demande internationale PCT/CN2021/120889
Date du dépôt international 27.09.2021
CIB
H01L 27/115 2017.1
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
27Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun
02comprenant des composants semi-conducteurs spécialement adaptés pour le redressement, l'amplification, la génération d'oscillations ou la commutation et ayant au moins une barrière de potentiel ou une barrière de surface; comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
04le substrat étant un corps semi-conducteur
10comprenant une pluralité de composants individuels dans une configuration répétitive
105comprenant des composants à effet de champ
112Structures de mémoires mortes
115Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
CPC
H01L 27/11519
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11519characterised by the top-view layout
H01L 27/11524
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
11524with cell select transistors, e.g. NAND
H01L 27/11551
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11551characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11565characterised by the top-view layout
H01L 27/1157
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
H01L 27/11578
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
Déposants
  • 长江存储科技有限责任公司 YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventeurs
  • 张中 ZHANG, Zhong
  • 韩玉辉 HAN, Yuhui
  • 孔翠翠 KONG, Cuicui
  • 张坤 ZHANG, Kun
Mandataires
  • 北京永新同创知识产权代理有限公司 NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Données relatives à la priorité
202011046857.929.09.2020CN
Langue de publication Chinois (zh)
Langue de dépôt chinois (ZH)
États désignés
Titre
(EN) THREE-DIMENSIONAL MEMORY AND MANUFACTURING METHOD THEREFOR
(FR) MÉMOIRE TRIDIMENSIONNELLE ET SON PROCÉDÉ DE FABRICATION
(ZH) 一种三维存储器及其制作方法
Abrégé
(EN) The present invention provides a three-dimensional memory and a manufacturing method therefor. The three-dimensional memory comprises a laminated structure, a dummy structure, and a gate line slit; wherein the laminated structure comprises gate line layers and isolation layers which are alternately stacked in a vertical direction; the dummy structure and the gate line slit both pass through the laminated structure in the vertical direction; the dummy structure comprises a first dummy portion and a second dummy portion; one end of the gate line slit extends into a gap formed by the first dummy portion and/or the second dummy portion; at least one of the first dummy portion and the second dummy portion partially overlaps the projection of the gate line slit on a horizontal plane, so as to implement connection of the dummy structure and the gate line slit. The design of the dummy structure which wraps the end portion of the gate line slit but is not completely overlapped with same can effectively mitigate the process window problem of gate line slit etching at a junction of the dummy structure and the gate line slit, can effectively reduce/eliminate weak points at the junction of the dummy structure and the gate line slit, and allows for improving the reliability of a device.
(FR) La présente invention concerne une mémoire tridimensionnelle et son procédé de fabrication. La mémoire tridimensionnelle comprend une structure stratifiée, une structure factice et une fente de ligne de grille ; la structure stratifiée comprenant des couches de ligne de grille et des couches d'isolation qui sont empilées en alternance dans une direction verticale ; la structure factice et la fente de ligne de grille passent toutes les deux à travers la structure stratifiée dans la direction verticale ; la structure factice comprend une première partie factice et une seconde partie factice ; une extrémité de la fente de ligne de grille s'étend dans un espace formé par la première partie factice et/ou la seconde partie factice ; la première partie factice et/ou la seconde partie factice chevauche partiellement la saillie de la fente de ligne de grille sur un plan horizontal, de façon à mettre en œuvre la connexion de la structure factice et de la fente de ligne de grille. La conception de la structure factice qui enveloppe la partie d'extrémité de la fente de ligne de grille mais n'est pas complètement chevauchée par celle-ci peut atténuer efficacement le problème de fenêtre de traitement de gravure de fente de ligne de grille au niveau d'une jonction de la structure factice et de la fente de ligne de grille, peut réduire/éliminer efficacement des points faibles au niveau de la jonction de la structure factice et de la fente de ligne de grille, et permet d'améliorer la fiabilité d'un dispositif.
(ZH) 本发明提供一种三维存储器及其制作方法,该三维存储器包括叠层结构、虚设结构及栅线缝隙,其中,叠层结构包括在垂直方向上交替堆叠的栅线层与隔离层,虚设结构及栅线缝隙均沿垂直方向贯穿叠层结构,虚设结构包括第一虚设部与第二虚设部,栅线缝隙的一端伸入由第一虚设部与/或第二虚设部形成的间隙中,第一虚设部与第二虚设部中的至少一个与栅线缝隙在水平面上的投影部分重叠,以实现虚设结构与栅线缝隙的连接。这种将栅线缝隙端部包裹住,但又不完全重叠的虚设结构设计可以有效改善虚设结构与栅线缝隙交界处栅线缝隙刻蚀的工艺窗口问题,有效减少/消除虚设结构与栅线缝隙交界处的脆弱点,有助于提高器件可靠性。
Documents de brevet associés
Dernières données bibliographiques dont dispose le Bureau international