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1. WO2021059046 - FORMATION DE TROUS D'INTERCONNEXION SUPÉRIEURS AUTO-ALIGNÉS AU NIVEAU D'EXTRÉMITÉS DE LIGNE

Numéro de publication WO/2021/059046
Date de publication 01.04.2021
N° de la demande internationale PCT/IB2020/057794
Date du dépôt international 19.08.2020
CIB
H01L 21/00 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
CPC
H01L 21/0335
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
033comprising inorganic layers
0334characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
0335characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
H01L 21/0337
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
033comprising inorganic layers
0334characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
0337characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
H01L 21/0338
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
033comprising inorganic layers
0334characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
0338Process specially adapted to improve the resolution of the mask
H01L 21/76885
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
H01L 21/76897
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
H01L 23/5226
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5226Via connections in a multilevel interconnection structure
Déposants
  • INTERNATIONAL BUSINESS MACHINES CORPORATION [US]/[US]
  • IBM UNITED KINGDOM LIMITED [GB]/[GB] (MG)
  • IBM (CHINA) INVESTMENT COMPANY LIMITED [CN]/[CN] (MG)
Inventeurs
  • ARNOLD, John
  • DUTTA, Ashim
  • METZLER, Dominik
  • DE SILVA, Ekmini, Anuja
Mandataires
  • WILLIAMS, Julian
Données relatives à la priorité
16/580,56724.09.2019US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) SELF-ALIGNED TOP VIA FORMATION AT LINE ENDS
(FR) FORMATION DE TROUS D'INTERCONNEXION SUPÉRIEURS AUTO-ALIGNÉS AU NIVEAU D'EXTRÉMITÉS DE LIGNE
Abrégé
(EN)
A method for fabricating a semiconductor device includes recessing a first odd hardmask and a first even hardmask to form recessed odd and even hardmasks, forming a first conductive hardmask including first conductive hardmask material on the recessed odd hardmask and a second conductive hardmask on the recessed even hardmask, and forming self-aligned vias at line ends corresponding to the first odd and even conductive lines based at least in part on the first and second conductive hardmasks.
(FR)
La présente invention concerne un procédé de fabrication d'un dispositif à semi-conducteur consistant à évider un premier masque dur impair et un premier masque dur pair pour former des masques durs impair et pair évidés, à former un premier masque dur conducteur comprenant un premier matériau de masque dur conducteur sur le masque dur impair évidé et un second masque dur conducteur sur le masque dur pair évidé et à former des trous d'interconnexion auto-alignés au niveau d'extrémités de ligne correspondant aux premières lignes impaire et paire sur la base, au moins en partie, des premier et second masques durs conducteurs.
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