Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

Aller à Demande

1. WO2021056513 - DISPOSITIFS DE MÉMOIRE TRIDIMENSIONNELS ET LEURS PROCÉDÉS DE FORMATION

Numéro de publication WO/2021/056513
Date de publication 01.04.2021
N° de la demande internationale PCT/CN2019/108891
Date du dépôt international 29.09.2019
CIB
H01L 27/115 2017.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
27Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun
02comprenant des composants semi-conducteurs spécialement adaptés pour le redressement, l'amplification, la génération d'oscillations ou la commutation et ayant au moins une barrière de potentiel ou une barrière de surface; comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
04le substrat étant un corps semi-conducteur
10comprenant une pluralité de composants individuels dans une configuration répétitive
105comprenant des composants à effet de champ
112Structures de mémoires mortes
115Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
CPC
H01L 27/11565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11565characterised by the top-view layout
H01L 27/1157
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
H01L 27/11578
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 29/40117
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
401Multistep manufacturing processes
4011for data storage electrodes
40117the electrodes comprising a charge-trapping insulator
H01L 29/42348
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
4234Gate electrodes for transistors with charge trapping gate insulator
42348with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
H01L 29/42376
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42372characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
42376characterised by the length or the sectional shape
Déposants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventeurs
  • ZHU, Hongbin
Mandataires
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Données relatives à la priorité
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
(FR) DISPOSITIFS DE MÉMOIRE TRIDIMENSIONNELS ET LEURS PROCÉDÉS DE FORMATION
Abrégé
(EN)
A 3D memory device (100) includes a substrate (102), a gate electrode (104) above the substrate (102), a blocking layer (106) on the gate electrode (104), a plurality of charge trapping layers (108a, 108b, 108c) on the blocking layer (106), a tunneling layer (110) on the plurality of charge trapping layers (108a, 108b, 108c), and a plurality of channel layers (112a, 112b, 112c) on the tunneling layer (110). The plurality of charge trapping layers (108a, 108b, 108c) are discrete and disposed at different levels. The plurality of channel layers (112a, 112b, 112c) are discrete and disposed at disposed at different levels. Each of the channel layers (112a, 112b, 112c) corresponds to a respective one of the charge trapping layers (108a, 108b, 108c).
(FR)
L'invention concerne un dispositif de mémoire 3D (100) comprenant un substrat (102), une électrode de grille (104) au-dessus du substrat (102), une couche de blocage (106) sur l'électrode de grille (104), une pluralité de couches de piégeage de charge (108a, 108b, 108c) sur la couche de blocage (106), une couche de tunnellisation (110) sur la pluralité de couches de piégeage de charge (108a, 108b, 108c), et une pluralité de couches de canal (112a, 112b, 112c) sur la couche de tunnellisation (110). La pluralité de couches de piégeage de charges (108a, 108b, 108c) sont discrètes et disposées à différents niveaux. La pluralité de couches de canal (112a, 112b, 112c) sont discrètes et disposées à des niveaux différents. Chacune des couches de canal (112a, 112b, 112c) correspond à une couche respective parmi les couches de piégeage de charges (108a, 108b, 108c).
Également publié en tant que
Dernières données bibliographiques dont dispose le Bureau international