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1. WO2020182357 - PROCÉDÉ DE FONCTIONNEMENT D'UN DISPOSITIF DE TRANSISTOR À SUPERJONCTION, ET DISPOSITIF DE TRANSISTOR À SUPERJONCTION

Numéro de publication WO/2020/182357
Date de publication 17.09.2020
N° de la demande internationale PCT/EP2020/051245
Date du dépôt international 20.01.2020
CIB
H03K 17/06 2006.01
HÉLECTRICITÉ
03CIRCUITS ÉLECTRONIQUES FONDAMENTAUX
KTECHNIQUE DE L'IMPULSION
17Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts
06Modifications pour assurer un état complètement conducteur
CPC
H01L 29/0634
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0611for increasing or controlling the breakdown voltage of reverse biased devices
0615by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
063Reduced surface field [RESURF] pn-junction structures
0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
H01L 29/407
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
402Field plates
407Recessed field plates, e.g. trench field plates, buried field plates
H01L 29/66734
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
66712Vertical DMOS transistors, i.e. VDMOS transistors
66734with a step of recessing the gate electrode, e.g. to form a trench gate electrode
H01L 29/7813
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
7802Vertical DMOS transistors, i.e. VDMOS transistors
7813with trench gate electrode, e.g. UMOS transistors
H03K 17/06
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and –breaking
06Modifications for ensuring a fully conducting state
H03K 17/687
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and –breaking
51characterised by the components used
56by the use, as active elements, of semiconductor devices
687the devices being field-effect transistors
Déposants
  • INFINEON TECHNOLOGIES AUSTRIA AG [AT]/[AT]
Inventeurs
  • HIRLER, Franz
  • FISCHER, Björn
  • KUTSCHAK, Matteo-Alessandro
  • RIEGLER, Andreas
  • WEBER, Hans
Mandataires
  • WESTPHAL MUSSGNUG & PARTNER
Données relatives à la priorité
19161485.808.03.2019EP
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) METHOD FOR OPERATING A SUPERJUNCTION TRANSISTOR DEVICE AND SUPERJUNCTION TRANSISTOR DEVICE
(FR) PROCÉDÉ DE FONCTIONNEMENT D'UN DISPOSITIF DE TRANSISTOR À SUPERJONCTION, ET DISPOSITIF DE TRANSISTOR À SUPERJONCTION
Abrégé
(EN)
A method and a transistor arrangement are disclosed. The method includes: applying a bias voltage (VDEP) different from zero between a drift region (11) and at least one of a compensation region (21) and a body region (22) of at least one transistor cell (10) of a transistor device when the transistor device is in a diode state, wherein the compensation region (21) has a doping type complementary to a doping type of the drift region (11), wherein the compensation region (21) adjoins the drift region (11), wherein a polarity of the bias voltage (VDEP) is such that a pn-junction between the drift region (11) and the at least one of the compensation region (21) and the body region (22) is reverse biased, wherein applying the bias voltage (VDEP) comprises applying the bias voltage (VDEP) between a bias region (4) that is coupled to the drift region (11) and the at least one of the compensation region (21) and the body region (22), and wherein the bias region (4) is spaced apart from a body region (22) and a source region (12) of the at least one transistor cell.
(FR)
La présente invention concerne un procédé et un agencement de transistor. Le procédé comprend : l'application d'une tension de polarisation (VDEP) différente de zéro entre une région de dérive (11) et au moins l'une parmi une région de compensation (21) et une région de corps (22) d'au moins une cellule de transistor (10) d'un dispositif de transistor lorsque le dispositif de transistor est dans un état de diode, la région de compensation (21) ayant un type de dopage complémentaire d'un type de dopage de la région de dérive (11), la région de compensation (21) étant adjacente à la région de dérive (11), une polarité de la tension de polarisation (VDEP) étant telle qu'une jonction pn entre la région de dérive (11) et l'au moins une parmi la région de compensation (21) et la région de corps (22) est polarisée en inverse, l'application de la tension de polarisation (VDEP) comprenant l'application de la tension de polarisation (VDEP) entre une région de polarisation (4) qui est couplée à la région de dérive (11) et l'au moins une parmi la région de compensation (21) et la région de corps (22), et la région de polarisation (4) étant espacée d'une région de corps (22) et d'une région de source (12) de l'au moins une cellule de transistor.
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