Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

Aller à Demande

1. WO2020117679 - DIODES PIN À RÉGIONS INTRINSÈQUES À ÉPAISSEURS MULTIPLES

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

[ EN ]

CLAIMS

Therefore, the following is claimed:

1. A semiconductor structure of diodes, comprising:

an N-type silicon substrate;

an intrinsic layer on the N-type silicon substrate;

a first P-type region formed to a first depth into the intrinsic layer; and

a second P-type region formed to a second depth into the intrinsic layer.

2. The semiconductor structure according to claim 1, wherein the first depth is greater than the second depth.

3. The semiconductor structure according to any one of claims 1-2, further comprising a dielectric layer on the intrinsic layer, the dielectric layer including a plurality of openings.

4. The semiconductor structure according to claim 3, wherein:

the first P-type region is formed through a first opening among the plurality of openings; and

the second P-type region is formed through a second opening among the plurality of openings.

5. The semiconductor structure according to claim 3, wherein a first width of a first opening among the plurality of openings is different than a second width of a second opening among the plurality of openings.

6. The semiconductor structure according to any one of claims 1-5, further comprising:

a third P-type region formed to a third depth into the intrinsic layer, wherein:

the first depth is greater than the second depth; and

the second depth is greater than the third depth.

7. The semiconductor structure according to any one of claims 1-6, further comprising a cathode contact formed on the N-type silicon substrate at a backside of the semiconductor structure.

8. The semiconductor structure according to any one of claims 1-7, further comprising:

a first anode contact formed on the first P-type region at a frontside of the semiconductor structure; and

a second anode contact formed on the second P-type region at the frontside of the semiconductor structure.

9. A semiconductor structure of diodes, comprising:

a first pedestal comprising an N-type silicon substrate, an intrinsic layer on the N-type silicon substrate, and a first P-type region formed to a first depth into the intrinsic layer; a second pedestal comprising the N-type silicon substrate, the intrinsic layer on the N-type silicon substrate, and a second P-type region formed to a second depth into the intrinsic layer; and

an insulator formed between the first pedestal and the second pedestal.

10. The semiconductor structure according to claim 9, wherein the first depth is greater than the second depth.

11. The semiconductor structure according to any one of claims 9-10, further comprising a dielectric layer on the intrinsic layer, the dielectric layer including a plurality of openings.

12. The semiconductor structure according to claim 11, wherein:

the first P-type region is formed through a first opening among the plurality of openings; and

the second P-type region is formed through a second opening among the plurality of openings.

13. The semiconductor structure according to claim 11, wherein a first width of a first opening among the plurality of openings is different than a second width of a second opening among the plurality of openings.

14. The semiconductor structure according to any one of claims 9-13, further comprising:

a third pedestal comprising the N-type silicon substrate, the intrinsic layer on the N-type silicon substrate, and a third P-type region formed to a third depth into the intrinsic layer, wherein:

the insulator is formed between the first pedestal, the second pedestal, and the third pedestal;

the first depth is greater than the second depth; and

the second depth is greater than the third depth.

15. The semiconductor structure according to any one of claims 9-14, further comprising:

a first cathode contact formed on the N-type silicon substrate for the first pedestal at a backside of the semiconductor structure; and

a second cathode contact formed on the N-type silicon substrate for the second pedestal at the backside of the semiconductor structure.

16. The semiconductor structure according to any one of claims 9-15, further comprising:

a first anode contact formed on the first P-type region at a frontside of the semiconductor structure; and

a second anode contact formed on the second P-type region at the frontside of the semiconductor structure.

17. A method of manufacture of a semiconductor structure, comprising:

providing an N-type semiconductor substrate;

providing an intrinsic layer on the N-type semiconductor substrate;

forming an insulating layer on the intrinsic layer;

forming a first opening in the insulating layer;

implanting a first P-type anode region to a first depth into the intrinsic layer through the first opening in the insulating layer;

after implanting the first anode region, forming a second opening in the insulating layer; and

implanting a second P-type anode region to a second depth into the intrinsic layer through the second opening in the insulating layer.

18. The method of manufacture according to claim 17, wherein the first depth is greater than the second depth.

19. The method of manufacture according to any one of claims 17-18, wherein a first width of the first opening is different than a second width of the second opening.

20. The method of manufacture according to any one of claims 17-19, further comprising:

after implanting the second anode region, forming a third opening in the insulating layer; and

implanting a third P-type anode region to a third depth into the intrinsic layer through the third opening in the insulating layer.

21. A semiconductor structure of diodes, comprising:

an P-type silicon substrate;

an intrinsic layer on the P-type silicon substrate;

a first N-type region formed to a first depth into the intrinsic layer; and

a second N-type region formed to a second depth into the intrinsic layer.

22. The semiconductor structure according to claim 21, wherein the first depth is greater than the second depth.

23. The semiconductor structure according to any one of claims 21-22, further comprising a dielectric layer on the intrinsic layer, the dielectric layer including a plurality of openings.

24. The semiconductor structure according to claim 23, wherein:

the first N-type region is formed through a first opening among the plurality of openings; and

the second N-type region is formed through a second opening among the plurality of openings.

25. The semiconductor structure according to claim 23, wherein a first width of a first opening among the plurality of openings is different than a second width of a second opening among the plurality of openings.

26. The semiconductor structure according to any one of claims 21-25, further comprising:

a third N-type region formed to a third depth into the intrinsic layer, wherein:

the first depth is greater than the second depth; and

the second depth is greater than the third depth.

27. The semiconductor structure according to any one of claims 21-26, further comprising a contact formed on the P-type silicon substrate at a backside of the semiconductor structure.

28. The semiconductor structure according to any one of claims 21-27, further comprising:

a contact formed on the first N-type region at a frontside of the semiconductor structure; and

a contact formed on the second N-type region at the frontside of the semiconductor structure.

29. A semiconductor structure of diodes, comprising:

a first pedestal comprising an P-type silicon substrate, an intrinsic layer on the P-type silicon substrate, and a first N-type region formed to a first depth into the intrinsic layer; a second pedestal comprising the P-type silicon substrate, the intrinsic layer on the P-type silicon substrate, and a second N-type region formed to a second depth into the intrinsic layer; and

an insulator formed between the first pedestal and the second pedestal.

30. The semiconductor structure according to claim 29, wherein the first depth is greater than the second depth.

31. The semiconductor structure according to any one of claims 29-30, further comprising a dielectric layer on the intrinsic layer, the dielectric layer including a plurality of openings.

32. The semiconductor structure according to claim 31, wherein:

the first N-type region is formed through a first opening among the plurality of openings; and

the second N-type region is formed through a second opening among the plurality of openings.

33. The semiconductor structure according to claim 31, wherein a first width of a first opening among the plurality of openings is different than a second width of a second opening among the plurality of openings.

34. The semiconductor structure according to any one of claims 29-33, further comprising:

a third pedestal comprising the P-type silicon substrate, the intrinsic layer on the P-type silicon substrate, and a third N-type region formed to a third depth into the intrinsic layer, wherein:

the insulator is formed between the first pedestal, the second pedestal, and the third pedestal;

the first depth is greater than the second depth; and

the second depth is greater than the third depth.

35. The semiconductor structure according to any one of claims 29-34, further comprising:

a first contact formed on the P-type silicon substrate for the first pedestal at a backside of the semiconductor structure; and

a second contact formed on the P-type silicon substrate for the second pedestal at the backside of the semiconductor structure.

36. The semiconductor structure according to any one of claims 29-35, further comprising:

a first contact formed on the first N-type region at a frontside of the semiconductor structure; and

a second contact formed on the second N-type region at the frontside of the semiconductor structure.

37. A method of manufacture of a semiconductor structure, comprising:

providing P-type semiconductor substrate;

providing an intrinsic layer on the P-type semiconductor substrate;

forming an insulating layer on the intrinsic layer;

forming a first opening in the insulating layer;

implanting a first N-type region to a first depth into the intrinsic layer through the first opening in the insulating layer;

after implanting the first anode region, forming a second opening in the insulating layer; and

implanting a second N-type region to a second depth into the intrinsic layer through the second opening in the insulating layer.

38. The method of manufacture according to claim 37, wherein the first depth is greater than the second depth.

39. The method of manufacture according to any one of claims 37-38, wherein a first width of the first opening is different than a second width of the second opening.

40. The method of manufacture according to any one of claims 37-39, further comprising:

after implanting the second anode region, forming a third opening in the insulating layer; and

implanting a third N-type region to a third depth into the intrinsic layer through the third opening in the insulating layer.