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1. (WO2019009872) TRANSISTOR EN COUCHES MINCES AUTO-ALIGNÉ À CONTACT SUPÉRIEUR ET À GRILLE ARRIÈRE
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

CLAIMS

What is claimed is:

1. A method of forming a thin- film transistor (TFT), comprising:

forming a TFT stack with a gate electrode layer, a gate dielectric layer formed over the gate electrode layer, and a TFT semiconductor layer formed over the gate dielectric layer;

forming a first backbone hardmask over the TFT stack;

forming spacers along sidewalls of the first backbone hardmask; forming first trenches into the TFT stack, wherein the first backbone hardmask and the spacers are used as an etch mask to define the trenches;

depositing a interlayer dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, wherein the second backbone hardmask is formed between the spacers;

removing the spacers;

forming second trenches into the material stack; and

forming source electrodes and drain electrodes in the trenches.

2. The method of claim 1, wherein the source electrodes and the drain electrodes are aligned with the TFT semiconductor layer.

3. The method of claim 2, wherein a sidewall of each of the source electrodes and drain electrodes is substantially coplanar with a sidewall surface of the TFT semiconductor layer.

4. The method of claim 1, further comprising:

forming an etch stop layer below the first backbone hardmask and the spacers.

5. The method of claim 1, further comprising:

forming a cap layer over a top surface of the first backbone hardmask and the spacers.

6. The method of claim 1, further comprising:

forming a first ILD layer over the material stack prior to forming the first backbone hardmask and the spacers.

7. The method of claim 1, wherein the TFT stack is formed over a lower ILD layer.

8. The method of claim 7, further comprising vias formed through the lower ILD layer.

9. The method of claim 8, wherein the vias contact an interconnect line below the lower ILD layer and the gate electrode layer.

The method of claim 9, further comprising:

forming trenches through the TFT stack, wherein the trenches run substantially parallel to the interconnect line.

The method of claim 9, wherein the trenches that run substantially parallel to the interconnect line are filled with an ILD.

The method of claim 1, wherein the TFT semiconductor layer is one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors.

13. The method of claim 1, wherein the TFT semiconductor layer has a thickness that is between approximately 5 nm and 50 nm.

14. The method of claim 1, wherein the source electrode and the drain electrode have the same dimensions.

15. A thin-film transistor (TFT) device, comprising:

a gate electrode;

a gate dielectric layer formed over a top surface of the gate electrode; a TFT semiconductor layer formed over a top surface of the gate dielectric layer; a source electrode formed over a top surface of the gate dielectric layer, wherein a sidewall of the source electrode is aligned with a first sidewall of the gate dielectric layer; and

a drain electrode formed over a top surface of the gate dielectric layer, wherein a sidewall of the drain electrode is aligned with a second sidewall of the gate dielectric layer.

16. The TFT device of claim 15, wherein an entire bottom surface of the source electrode and an entire bottom surface of the drain electrode contact a top surface of the TFT semiconductor layer.

17. The TFT device of claim 15, further comprising:

an interlayer dielectric (ILD) material formed between the source electrode and the drain electrode, wherein the ILD has a top surface that is substantially coplanar with a top surface of the source electrode and the drain electrode.

18. The TFT device of claim 15, further comprising:

an ILD layer formed below a bottom surface of the gate electrode.

19. The TFT device of claim 18, wherein a via is formed through the ILD layer, and wherein the via contacts a surface of the gate electrode.

20. The TFT device of claim 19, wherein the via contacts an interconnect line formed below the ILD layer.

21. The TFT device of claim 15, wherein the TFT semiconductor layer is one or more of InGaZnO, amorphous Ge, amorphous Si, ZnO, and polymer/organic semiconductors.

22. The TFT device of claim 15, wherein the TFT semiconductor layer that has a thickness that is between approximately 5 nm and approximately 50 nm.

23. The TFT device of claim 15, wherein the source electrode and the drain electrode have the same dimensions.

24. A method of forming a thin-film transistor, comprising:

forming a TFT stack with a gate electrode layer, a gate dielectric layer formed over the gate electrode layer, and a TFT semiconductor layer formed over the gate dielectric layer;

forming a first backbone hardmask over the TFT stack;

forming spacers along sidewalls of the first backbone hardmask; forming a cap layer over a top surface of the backbone hardmask; forming first trenches into the TFT stack, wherein the first backbone hardmask and the spacers are used as an etch mask to define the trenches;

depositing a interlayer dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, wherein the second backbone hardmask is formed between the spacers;

removing the spacers;

forming second trenches into the material stack; and

forming source electrodes and drain electrodes in the trenches, wherein a sidewall of each of the source electrodes and drain electrodes is substantially coplanar with a sidewall surface of the TFT semiconductor layer, and wherein the source electrode and the drain electrode have the same dimensions.

The method of claim 24, wherein an entire bottom surface of the source electrode and entire bottom surface of the drain electrode contact a top surface of the TFT

semiconductor layer.