Certains contenus de cette application ne sont pas disponibles pour le moment.
Si cette situation persiste, veuillez nous contacter àObservations et contact
1. (WO2019005220) DISPOSITIF DE MÉMOIRE TRIDIMENSIONNEL CONTENANT UNE COUCHE BARRIÈRE DE DIFFUSION D'HYDROGÈNE POUR CMOS SOUS UNE ARCHITECTURE DE RÉSEAU ET SON PROCÉDÉ DE FABRICATION
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

WHAT IS CLAIMED IS:

1. A semiconductor structure, comprising:

at least one semiconductor device;

a dielectric layer stack of at least one first dielectric material layer, a silicon nitride layer comprising a hydrogen diffusion barrier, and at least one second dielectric material layer overlying the at least one semiconductor device;

lower metal interconnect structures embedded within the dielectric layer stack, the lower metal interconnect structures comprising a lower metal line structure located below the silicon nitride layer;

a three-dimensional memory array overlying the dielectric layer stack and including an alternating stack of insulating layers and electrically conductive layers, and including memory stack structures vertically extending through the alternating stack in a memory array region;

a through-stack contact via structure extending through the alternating stack, through the at least one second dielectric material layer, and through the silicon nitride layer, and contacting the lower metal line structure; and

a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack and through the at least one second dielectric material layer, but not extending through the silicon nitride layer.

2. The semiconductor structure of Claim 1, further comprising upper metal interconnect structures including an upper metal line structure, located over the three-dimensional memory array.

3. The semiconductor structure of Claim 2, wherein:

the at least one semiconductor device comprises a CMOS driver circuit device located on a top surface of a substrate semiconductor layer of a substrate or on a top surface of the substrate;

the lower metal line structure contacts a bottom surface of the silicon nitride layer; the through-stack contact via structure contacts a top surface of the lower metal line structure and a bottom surface of the upper metal line structure,

a set of conductive structures including the through-stack contact via structure and the lower metal line structure provides an electrically conductive path between the at least one semiconductor device and the upper metal line structure;

an inner sidewall of the through-stack insulating spacer contacts a sidewall of the through-stack contact via structure; and

an outer sidewall of the through-stack insulating spacer contacts sidewalls of each layer within the alternating stack.

4. The semiconductor structure of Claim 1, further comprising a planar semiconductor material layer located between the at least one second dielectric material layer and the alternating stack, wherein the through- stack insulating spacer vertically extends through an opening in the planar semiconductor material layer and through at least an upper portion of the at least one second dielectric material layer.

5. The semiconductor structure of Claim 4, wherein:

each of the memory stack structures includes a memory film and a vertical semiconductor channel that extend through the alternating stack; and

the planar semiconductor material layer includes a horizontal semiconductor channel that is electrically connected to the vertical semiconductor channels of the memory stack structures.

6. The semiconductor structure of Claim 4, wherein the through-stack insulating spacer is laterally spaced from a sidewall of the opening of the planar semiconductor material layer by a portion of the at least one second dielectric material layer.

7. The semiconductor structure of Claim 1, wherein:

the through-stack insulating spacer directly contacts a top surface silicon nitride layer but does not extend through the entire thickness of the silicon nitride layer; and

the through-stack contact via structure is laterally spaced from the at least one second dielectric material layer by the through- stack insulating spacer.

8. The semiconductor structure of Claim 1, wherein:

the through-stack insulating spacer does not directly contact the silicon nitride layer; and

the through-stack contact via structure directly contacts the at least one second dielectric material layer.

9. The semiconductor structure of Claim 1, further comprising:

a terrace region including stepped surfaces of layers of the alternating stack;

a retro- stepped dielectric material portion overlying the stepped surfaces and located at levels of the alternating stack and above the at least one second dielectric material layer; and

a through-dielectric contact via structure vertically extending through the retro-stepped dielectric material portion, the at least one second dielectric material layer, and the silicon nitride layer and contacting a top surface of another lower metal line structure of the lower metal interconnect structures,

wherein the through-dielectric contact via structure directly contacts the retro-stepped dielectric material portion and the at least one second dielectric material layer.

10. The semiconductor structure of Claim 1, wherein:

the three-dimensional memory array comprises a monolithic three-dimensional NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the planar semiconductor material layer comprises a polysilicon layer;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the polysilicon layer;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the at least one semiconductor device comprises an integrated circuit comprising a

driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises:

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

11. A semiconductor structure, comprising:

a semiconductor device;

a hydrogen diffusion barrier layer;

a lower metal line structure located below the hydrogen diffusion barrier layer;

an alternating stack of insulating layers and electrically conductive layers;

memory stack structures vertically extending through the alternating stack in a memory array region;

a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure; and

a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer.

12. A method of forming a semiconductor structure, comprising:

forming at least one semiconductor device;

forming dielectric layer stack comprising at least one first dielectric material layer, a silicon nitride layer, and at least one second dielectric material layer over the at least one semiconductor device;

forming lower metal interconnect structures embedded within the dielectric layer stack, and comprising a lower metal line structure located below the silicon nitride layer; forming a first alternating stack of insulating layers and sacrificial material layers over the dielectric layer stack and over the lower metal interconnect structures;

forming memory stack structures vertically extending through the first alternating stack in a memory array region;

forming a first through- stack via cavity through the first alternating stack in the memory array region, wherein a bottom surface of the first through- stack via cavity is formed at, or above, the silicon nitride layer;

depositing a dielectric material in the first through-stack via cavity to form a through-stack insulating material portion;

replacing the sacrificial material layers in the first alternating stack with electrically conductive layers to form a second alternating stack of insulating layers and electrically conductive layers after forming the through-stack insulating material portion;

forming a second through-stack via cavity through the through-stack insulating material portion and through the silicon nitride layer after forming the second alternating stack, wherein a remaining portion of the through-stack insulating material portion after formation of the second through-stack via cavity constitutes a through-stack insulating spacer; and

forming the through-stack contact via structure within the second through-stack via cavity and inside the through-stack insulating spacer in contact with the lower metal line structure.

13. The method of Claim 12, wherein the second through-stack via cavity is formed through the silicon nitride layer such that the lower metal line structure is physically exposed in second through-stack via cavity.

14. The method of Claim 13, wherein:

the silicon nitride layer is formed by chemical vapor deposition using a dichlorosilane precursor; and

the second through-stack via cavity is formed employing an anisotropic etch process that includes a first etch step that etches the dielectric material of the through-stack insulating material portion selective to the silicon nitride layer, and a second etch step that etches a physically exposed portion of the silicon nitride layer.

15. The method of Claim 13, further comprising:

forming a terrace region including stepped surfaces by patterning layers of the first

alternating stack;

forming a retro- stepped dielectric material portion over the stepped surfaces at levels of the first alternating stack and above the at least one second dielectric material layer; and forming a through-dielectric contact via structure through the retro-stepped dielectric material portion, through the at least one second dielectric material layer, and through the silicon nitride layer and directly on another lower metal line structure of the lower metal interconnect structures.

16. The method of Claim 15, wherein:

each of the memory stack structures includes a memory film and a vertical semiconductor channel; and

the through-dielectric contact via structure is formed after forming the second alternating stack.

17. The method of Claim 16, wherein the through-dielectric contact via structure is formed by:

forming a through-dielectric via cavity concurrently with formation of the second through-stack via cavity employing a same anisotropic etch process;

simultaneously depositing a conductive material in the through-dielectric via cavity and in the second through-stack via cavity; and

removing excess portions of the conductive material from outside the through-dielectric via cavity and in the second through-stack via cavity, wherein remaining portions of the conductive material constitutes the through-dielectric contact via structure and the through-stack contact via structure.

18. The method of Claim 12, further comprising forming upper metal interconnect structures over the second alternating stack, wherein the upper metal interconnect structures comprises an upper metal line structure that is formed directly on the through- stack contact via structure.

19. The method of Claim 18, wherein:

the at least one semiconductor device comprises a CMOS driver circuit device located on a top surface of a substrate semiconductor layer of a substrate or on a top surface of the substrate; and

a set of conductive structures including the through-stack contact via structure and the lower metal line structure provides an electrically conductive path between the at least one semiconductor device and the upper metal line structure.

20. The method of Claim 12, wherein:

the three-dimensional memory array comprises a monolithic three-dimensional NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the planar semiconductor material layer comprises a polysilicon layer;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the polysilicon layer;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the at least one semiconductor device comprises an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises:

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.