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1. (WO2019005002) DISPOSITIF DE DÉCALAGE DE NIVEAU
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

Claims:

1. A level shifter, comprising :

a first ferroelectric capacitor;

a first node of the first ferroelectric capacitor, comprising an input voltage node;

a second capacitor; and

a shared node of the first ferroelectric capacitor and second capacitor, comprising an output voltage node.

2. The level shifter of claim 1, wherein the first ferroelectric capacitor has plate-to-plate distance of approximately 25 nm.

3. The level shifter of claim 1, wherein the first ferroelectric capacitor has a plate-to-plate distance in a range of approximately 25 nm - 40nm .

4. The level shifter of claim 1, wherein the first ferroelectric capacitor has a lateral area of approximately 0.25 μηι2.

5. The level shifter of claim 1, wherein the first ferroelectric capacitor has a lateral area in a range of approximately 0.125 - 0.40 μηι2.

6. The level shifter of any of claims 1 - 5, further comprising an input voltage in a first voltage domain at the input node, wherein the first ferroelectric capacitor is configured to operate in a negative capacitance region at the input voltage and to shift the input voltage to a second voltage domain at the output node.

7. The level shifter of any of claims 1 - 5, wherein the second capacitor is a second ferroelectric capacitor.

8. The level shifter of claim 7, wherein the second ferroelectric capacitor is configured to operate in a positive capacitance region at an operational voltage of the input voltage signal .

9. The level shifter of any of claims 1 - 5, wherein the first ferroelectric capacitor comprises a ferroelectric material of HfZrO.

10. An integrated circuit, comprising :

a first logic circuit to operate in a first voltage domain;

a second logic circuit to operate in a second voltage domain; and

the level shifter of any of claims 1 - 5, wherein the level shifter is configured to shift an input voltage from the first voltage domain to an output voltage for the second voltage domain.

11. An integrated circuit, comprising :

a first logic circuit configured to operate at a first voltage level;

a second logic circuit communicatively coupled to the first logic circuit and configured to operate at a second voltage level; and

a level shifter, comprising :

a first ferroelectric capacitor;

an input voltage signal applied to a first node of the first ferroelectric capacitor;

a second capacitor; and

an output voltage signal at a shared node of the first ferroelectric capacitor and second capacitor.

12. The integrated circuit of claim 11, wherein the second logic circuit comprises an embedded flash device.

13. The integrated circuit of claim 11, wherein the second logic circuit comprises a tunneling transistor.

14. The integrated circuit of claim 11, wherein the second logic circuit comprises a negative capacitance transistor.

15. The integrated circuit of claim 11, wherein the second logic circuit comprises a two-dimensional material device.

16. The integrated circuit of claim 11, wherein the second logic circuit comprises a magnetic memory device.

17. The integrated circuit of claim 11, wherein the second logic circuit comprises a resistive memory device.

18. The integrated circuit of claim 11, wherein the second logic circuit comprises a ferroelectric memory device.

19. The integrated circuit of any of claims 11 - 18, further comprising a filtering circuit electrically located between the first logic circuit and the second logic circuit.

20. The integrated circuit of claim 19, wherein the filtering circuit is an RC circuit.

21. The integrated circuit of any of claims 11 - 18, wherein the first ferroelectric capacitor comprises a ferroelectric material of HfZrO.

22. A method of manufacturing an integrated circuit, comprising :

forming a first logic circuit configured to operate at a first voltage level;

forming a second logic circuit configured to operate at a second voltage level;

forming a level shifter, comprising :

a first ferroelectric capacitor;

an input voltage signal applied to a first node of the first ferroelectric capacitor;

a second ferroelectric capacitor; and

an output voltage signal at a shared node of the first ferroelectric capacitor and second ferroelectric capacitor.

23. The method of claim 22, wherein the first ferroelectric capacitor has plate-to-plate distance of 25 nm.

24. The method of claim 22, wherein the first ferroelectric capacitor has a lateral area of 0.25 μηι2.

25. The method of claim 22, wherein the first ferroelectric capacitor is configured to operate in a negative capacitance region at an operational voltage of the input voltage signal .