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1. (WO2018226360) AMPLIFICATEUR ET ÉGALISEUR À TEMPS CONTINU À TROIS ENTRÉES DESTINÉS À UNE SIGNALISATION À NIVEAUX MULTIPLES
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Claims

We claim:

1. A receiver equalizer for a three-level signaling system, comprising:

a first transistor arranged in parallel with a second transistor and with a third transistor, wherein a gate for the first transistor is configured to receive a first signal, a gate for the second transistor is configured to receive a second signal, and a gate for the third transistor is configured to receive a third signal;

a first current source configured to bias a first terminal of the first transistor;

a second current source configured to bias a first terminal of the second transistor; a third current source configured to bias a first terminal of the third transistor;

a first equalizing pair of a capacitor and a resistor connected to the first terminal of the first transistor;

a second equalizing pair of a capacitor and a resistor connected to the first terminal of the second transistor; and

a third equalizing pair of a capacitor and a resistor connected to the first terminal of the third transistor.

2. The receiver equalizer of claim 1 , wherein the first transistor, the second transistor, and the third transistor are p-type metal oxide semiconductor (PMOS) transistors.

3. The receiver equalizer of claim 1 , further comprising:

a first resistor to a second terminal of the first transistor;

a second resistor connected to a second terminal of the second transistor; and a third resistor coupled between a second terminal of the third transistor.

4. The receiver equalizer of claim 3, wherein the first resistor, the second resistor, and the third resistor are all connected to ground.

5. The receiver equalizer of claim 1 , wherein the first transistor is matched to the second transistor and to the third transistor.

6. The receiver equalizer of claim 1, wherein the first equalizing pair, the second equalizing pair, and the third equalizing pair are all connected to a common node.

7. The receiver equalizer of claim 1 , wherein the first equalizing pair is also connected to the first terminal of the second transistor.

8. The receiver equalizer of claim 7, wherein the second equalizing pair is also connected to the first terminal of the third transistor.

9. The receiver equalizer of claim 8, wherein the third equalizing pair is also connected to the first terminal of the first transistor.

10. A method, comprising:

weakly switching on a first transistor responsive to a first input signal to produce a low output voltage at a first terminal of the first transistor;

switching on a second transistor responsive to a second input signal to produce a high output voltage at a first terminal of the second transistor;

partially switching on a third transistor responsive to a third input signal to produce a mid-range output voltage at a terminal of the third transistor, wherein the high voltage is greater than the mid-range voltage, and the mid-range voltage is greater than the low voltage; and

boosting a high-frequency gain with respect to a difference between the high output voltage and the low output voltage by conducting charge from a second terminal of the first transistor to a second terminal of the second transistor through a first equalizing pair of a capacitor and a resistor.

11. The method of claim 10, further comprising

boosting a high frequency gain with respect to a difference between the mid-range output voltage and the low output voltage by conducting charge from the second terminal of the first transistor to a second terminal of the third transistor through a second equalizing pair of a capacitor and a resistor.

12. The method of claim 11 , further comprising:

boosting a high-frequency gain with respect to a difference between the high output voltage and the mid-range output voltage by conducting charge from the second terminal of the third transistor to the second terminal of the second transistor through a third equalizing pair of a capacitor and a resistor.

13. The method of claim 10, further comprising

driving a first current into the second terminal of the first transistor, wherein producing the low output voltage at the first terminal of the first transistor comprises

conducting a portion of the first current through a resistor connected to the second terminal of the first transistor.

14. The method of claim 13, further comprising:

driving a second current into the second terminal of the second transistor; and driving a third current into the third terminal of the third transistor.

15. The method of claim 10, further comprising:

amplifying a trio of received signals for a three-level signaling system to produce the first signal, the second signal, and the third signal.

16. A method for a three-level signaling system, comprising:

driving a current into a node shared by a first transistor, a second transistor, and a third transistor;

while receiving the current at the node:

weakly switching on the first transistor responsive to a first input signal to produce a low voltage signal at a terminal of the first transistor by conducting a first portion of the current through the first transistor, wherein the low voltage signal is an amplified version of the first input signal;

switching on the second transistor responsive to a second input signal to produce a high voltage signal at a terminal of the second transistor by conducting a second portion of the current through the second transistor, wherein the high voltage signal is an amplified version of the second input signal; and

partially switching on the third transistor responsive to a third input signal to produce a mid-range voltage signal at a terminal of the third transistor by conducting a third portion of the current through the third transistor, wherein the mid-range voltage signal is an amplified version of the third input signal, the third portion is greater than the first portion, the second portion is greater than the third portion, the high voltage signal is greater than the mid-range voltage signal, and the mid-range voltage signal is greater than the low voltage signal.

17. The method of claim 16, wherein producing the high voltage signal at the terminal of the second transistor comprises conducting the second portion of the current through a resistor connected to the terminal of the second transistor.

18. The method of claim 16, wherein producing the mid-range voltage signal at the terminal of the third transistor comprises conducting the third portion of the current through a resistor connected to the terminal of the third transistor.

19. The method of claim 16, wherein driving a current into the node shared by the first transistor, the second transistor, and the third transistor comprises driving the current into a source terminal for the first transistor, a source terminal for the second transistor, and a source terminal for the third transistor.

20. The method of claim 16, wherein producing the low voltage signal at the terminal of the first transistor comprises conducting the first portion of the current through a resistor connected to the terminal of the first transistor.