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1. (WO2018204487) EMPILEMENT DE PUCES SEMI-CONDUCTRICES À GRANDE VITESSE
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

CLAIMS

What is claimed is:

1. A high-speed semiconductor chip stack forming an electrical circuit comprising one or more physical layers of perovskite electroceramic that functions as a capacitive dielectric material and said one or more physical layers are integrated as part of at least one surface feature on a semiconductor die or an interposer embedded within the high speed semiconductor chip stack wherein the perovskite electroceramic forming said capacitive dielectric material further comprises a uniform distribution of ceramic grains with a grain size diameter less than 50 nm such that orbital deformations constitute the sole mechanism contributing to the dielectric polarization within said capacitive dielectric material.

2. The high-speed semiconductor chip stack of claim 1, wherein the capacitive dielectric material has dielectric polarization rates measured on femto-second time scales.

3. The high-speed semiconductor chip stack of claim 1, wherein the perovskite

electroceramic and has a relative permittivity SR > 70.

4. The high-speed semiconductor chip stack of claim 3, wherein the high energy density capacitive dielectric material has a relative permittivity, SR, in the range of 200 < SR < 800.

5. The high-speed semiconductor chip stack of claim 1, wherein the capacitive dielectric material comprises a thermodynamically stable perovskite electroceramic.

6. The high-speed semiconductor chip stack of claim 5, wherein the thermodynamically stable perovskite electroceramic may comprise titanate, zirconate, hafnate, niobate, or tantalate electroceramic, or admixture thereof.

7. The high-speed semiconductor chip stack of claim 6, wherein thermodynamically stable perovskite electroceramic comprises an admixture of three (3) or more elements from the group comprising: scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), zinc (Zn), zirconium (Zr), niobium (Nb), molybdenum (Mo),

hafnium (Hf), tantalum (Ta), tungsten (W), lanthanum (La), cerium (Ce),

praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dionysium (Dy), holomium (Ho), ytterbium (Yb), indium (In), tin (Sn), lead (Pb), or bismuth (Bi).

8. The high-speed semiconductor chip stack of claim 3, wherein the perovskite

electroceramic has a crystal lattice with an average atomic mass unit (amu) that is greater than 25.

9. The high-speed semiconductor chip stack of claim 8, wherein the crystal lattice has an average atomic mass unit (amu) that is greater than 50.

10. The high-speed semiconductor chip stack of claim 1, wherein the surface feature is deployed to terminate an electrical discontinuity in the electrical circuit.

11. The high-speed semiconductor chip stack of claim 10, wherein the surface feature is deployed along a transmission line.

12. The high-speed semiconductor chip stack of claim 11, wherein the surface feature and transmission line are deployed on a semiconductor die.

13. The high-speed semiconductor ship stack of claim 11, wherein the surface feature and transmission line are deployed on an interposer.

14. The high-speed semiconductor chip stack of claim 10, wherein the surface feature is deployed at a via.

15. The high-speed semiconductor chip stack of claim 14, wherein the surface feature and the via are deployed on a semiconductor die.

16. The high-speed semiconductor chip stack of claim 14, wherein the surface feature and the via are deployed on an interposer.

17. The high-speed semiconductor chip stack of claim 1, wherein the at least one surface feature minimizes the reflections of higher frequency harmonics of the digital signal pulse such that the operational system clock speed of the high-speed semiconductor chip stack optimally matches the slowest clock speed of the semiconductor die embedded within the high speed semiconductor chip stack.

18. The high-speed semiconductor chip stack of claim 17, wherein one or more embedded semiconductor die perform an optical or electro-optical circuit function.

19. The high-speed semiconductor chip stack of claim 17, wherein one or more embedded semiconductor die is a component of a wireless transmitter, wireless receiver, or wireless transceiver circuit module.

20. The capacitive dielectric layer of claim 1, wherein the composition of the perovskite electroceramic is doped with < 0.05 mol% of silicon dioxide that forms electrically insulating metal oxide phases at the nanoscale grain boundaries within the perovskite electroceramic to neutralize the formation of internal conductive pathways and dissipation currents within the capacitive dielectric material.