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1. (WO2018140104) PROCÉDÉ ET SYSTÈME DE PRÉDICTION DE DÉFAUTS DE CIRCUITS INTÉGRÉS
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

What is claimed is:

1. A method for defect prediction, comprising:

receiving feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC; and

determining a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system.

2. The method of claim 1, further comprising:

receiving design data comprising a layout of the IC; and

performing lithography simulation using the design data to determine the feature data.

3. The method of claim 2, wherein the feature data includes any of a polygon determined from the design data, a rendered image determined from the polygon, and a processed image determined from the rendered image.

4. The method of claim 1, wherein

the process condition data includes any of a focus condition of the production process and a dose condition of the production process, and

the defect prediction technique includes any of a parameter associated with focus conditions, a parameter associated with dose conditions, a parameter associated with etching, and a parameter associated with chemical-mechanical planarization (CMP).

5. The method of claim 1, wherein the high-resolution inspection system comprises an electron beam inspection system.

6. The method of claim 1, further comprising:

determining, by the high-resolution inspection system, an inspection result by inspecting the care area; and

updating a parameter of the defect prediction technique based on the inspection result.

7. The method of claim 1, further comprising:

receiving test feature data and test process condition data both associated with a defective IC area and a non-defective IC area, wherein the defective IC area includes a defect determined by the high-resolution inspection system and the non-defective IC area does not include a defect; and

determining a parameter of the defect prediction technique based on the test feature data and the test process condition data.

8. A system for defect prediction, comprising:

a processor; and

a memory coupled to the processor, the memory configured to store a set of instructions which when executed by the processor become operational with the processor to:

receive feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC; and

determine a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system.

9. The system of claim 8, wherein the memory is configured to store further instructions when executed by the processor become operational with the processor to:

receive design data comprising a layout of the IC; and

perform lithography simulation using the design data to determine the feature data.

10. The system of claim 9, wherein the feature data includes any of a polygon determined from the design data, a rendered image determined from the polygon, and a processed image determined from the rendered image.

11. The system of claim 8, wherein

the process condition data includes any of a focus condition of the production process and a dose condition of the production process, and

the defect prediction technique includes any of a parameter associated with focus conditions, a parameter associated with dose conditions, a parameter associated with etching, and a parameter associated with chemical-mechanical planarization (CMP).

12. The system of claim 8, wherein the memory is configured to store further instructions when executed by the processor become operational with the processor to:

determine, by the high-resolution inspection system, an inspection result by inspecting the care area; and

update a parameter of the defect prediction technique based on the inspection result.

13. The system of claim 8, wherein the memory is configured to store further instructions when executed by the processor become operational with the processor to:

receive test feature data and test process condition data both associated with a defective IC area and a non-defective IC area, wherein the defective IC area includes a defect determined by the high-resolution inspection system and the non-defective IC area does not include a defect; and

determine a parameter of the defect prediction technique based on the test feature data and the test process condition data.

14. A non-transitory computer-readable medium storing a set of instructions which when executed by a computer system using a processor become operational with the processor for defect prediction, the non- transitory computer-readable medium comprising instructions to: receive, during a production process associated with an integrated circuit (IC), feature data of the IC and process condition data of the production process; and

determine, during the production process, a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system.

15. The computer-readable medium of claim 14, comprising further instructions to: receive design data comprising a layout of the IC; and

perform lithography simulation using the design data to determine the feature data.

16. The computer-readable medium of claim 15, wherein the feature data includes any of a polygon determined from the design data, a rendered image determined from the polygon, and a processed image determined from the rendered image.

17. The computer-readable medium of claim 14, wherein

the process condition data includes any of a focus condition of the production process and a dose condition of the production process, and

the defect prediction technique includes any of a parameter associated with focus

conditions, a parameter associated with dose conditions, a parameter associated with etching, and a parameter associated with chemical-mechanical planarization (CMP).

18. The computer-readable medium of claim 14, wherein the high-resolution inspection system comprises an electron beam inspection system.

19. The computer-readable medium of claim 14, comprising further instructions to: determine, by the high-resolution inspection system, an inspection result by inspecting the care area; and

update a parameter of the defect prediction technique based on the inspection result.

20. The computer-readable medium of claim 14, comprising further instructions to: receive test feature data and test process condition data both associated with a defective IC area and a non-defective IC area, wherein the defective IC area includes a defect determined by the high-resolution inspection system and the non-defective IC area does not include a defect; and

determine a parameter of the defect prediction technique based on the test feature data and the test process condition data.