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1. (WO2018125499) PONT DE TRANSMISSION À ANNULATION DE DIAPHONIE
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

What is claimed:

1. A connecting card for use in a memory connector, comprising:

a substrate including a first substrate region and a second substrate region; a plurality of adjacent signal pathways extending from the first substrate region to the second substrate region; and

a capacitor positioned between each of the adjacent signal pathways.

2. The connection card of claim 1, wherein the capacitor comprises a discrete capacitor coupled to the substrate.

3. The connecting card of claim 1, wherein the substrate comprises a plurality of layers and the capacitor is positioned in one or more of the layers.

4. The connecting card of claim 1, wherein the capacitor is embedded in the substrate.

5. The connecting card of claim 1, wherein the plurality of adjacent signal pathways include a first signal pathway adjacent to a second signal pathway, and a third signal pathway adjacent to the second signal pathway, wherein a first capacitor is positioned between the first signal pathway and the second signal pathway, wherein a second capacitor is positioned between the second signal pathway and the third signal pathway, and wherein a third capacitor is positioned between the first signal pathway and the third signal pathway.

6. The connecting card of claim 1, further comprising at least one additional capacitor positioned between two of the signal pathways.

7. The connecting card of any one of claims 1-6, wherein the connecting card includes a first side and a second side, wherein the first substrate region is positioned on the first side, and wherein the second substrate region is positioned on the second side.

8. A system comprising:

a memory controller;

a memory region including a first memory connector and a second memory connector;

a channel for delivering data between the memory controller and the memory region, the channel including a first group of signal pathways and a second group of signal pathways;

the first group of signal pathways configured to bypass the first memory connector and extend to the second memory connector;

the second group of signal pathways each including a first region that extends to the first memory connector and a second region that extends from the first memory connector to the second memory connector;

a connecting card positioned in the first memory connector, the connecting card configured to route signals from the first region through the connecting card to the second region, the connecting card comprising a substrate including a first substrate region and a second substrate region, a plurality of adjacent signal pathways extending from the first substrate region to the second substrate region, and a capacitor positioned between each of the adjacent signal pathways; and

a memory module positioned in the second memory connector, wherein the memory module is configured to receive data signals from the first group of signal pathways and from the second group of signal pathways.

9. The system of claim 8, wherein the capacitor comprises a discrete capacitor coupled to the substrate.

10. The system of claim 8, wherein the substrate comprises a plurality of layers and the capacitor is positioned in one or more of the layers.

11. The system of claim 8, wherein the capacitor is embedded in the substrate.

12. The system of claim 8, wherein the plurality of adjacent signal pathways in the connecting card include a first signal pathway adjacent to a second signal pathway, and a third signal pathway adjacent to the second signal pathway, wherein a first capacitor is positioned between the first signal pathway and the second signal pathway, wherein a second capacitor is positioned between the second signal pathway and the third signal pathway, and wherein a third capacitor is positioned between the first signal pathway and the third signal pathway.

13. The system of claim 8, wherein the connecting card further comprises at least one additional capacitor positioned between two of the signal pathways.

14. The system of claim 8, wherein the signal pathways in the channel comprise even byte lanes and odd byte lanes, wherein the first group of signal pathways includes the even byte lanes, and wherein the second group of signal pathways includes the odd byte lanes.

15. The system of any one of claims 8-14, wherein the connecting card includes a first side and a second side, wherein the first substrate region is positioned on the first side, and wherein the second substrate region is positioned on the second side.

16. The system of any one of claims 8-14, wherein the memory module comprises a dual in-line memory module (DIMM).

17. The system of claim 16, wherein the DIMM comprises dynamic random access memory (DRAM).

18. A method for transmitting data in a system comprising:

configuring a channel for delivering data between a memory controller and a memory region, the memory region including a first connector and a second connector, the channel configured to include a first group of signal pathways and a second group of signal pathways;

positioning the first group of signal pathways to extend to the second connector;

positioning the second group of signal pathways to include a first region extending to the first connector and a second region extending from the first connector to the second connector;

positioning a connecting card in the first connector, the connecting card configured to route signals from the first region through the connecting card to the second region, the connecting card comprising a substrate including a first substrate region and a second substrate region, a plurality of adjacent signal pathways extending from the first substrate region to the second substrate region, and a capacitor positioned between each of the adjacent signal pathways; and

positioning a memory module in the second connector, wherein the memory module is configured to receive data signals from the first group of signal pathways and from the second group of signal pathways; and wherein the data signals from the first group of signal pathways do not travel through the connecting card.

19. The method of claim 18, comprising configuring the channel so that the signal pathways in the channel comprise even byte lanes and odd byte lanes, wherein the first group of signal pathways includes the even byte lanes, and wherein the second group of signal pathways includes the odd byte lanes.

20. The method of any one of claims 18-19, further comprising positioning at least one additional capacitor between two of the signal pathways the connecting card.

21. The method of any one of claims 18-19, wherein the capacitor positioned between each of the adjacent signal pathways on the connecting card is provided by embedding the capacitor in the substrate.

22. A method for decreasing crosstalk in a connecting card having a plurality of adjacent signal pathways, comprising positioning a capacitor between each of the adjacent signal pathways.

23. The method of claim 22, further comprising positioning the connecting card between a memory controller and a memory module in a computing system.

24. An apparatus comprising:

means for routing a plurality of signal pathways on a substrate from a first substrate region to a second substrate region; and

means for positioning a capacitor between adjacent signal pathways of the plurality of signal pathways on the substrate.

25. An apparatus comprising means to perform a method as claimed in any preceeding claim.