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1. (WO2018125159) BOÎTIER DE SEMICONDUCTEUR AYANT UNE LIAISON FILAIRE SINGULIÈRE SUR DES PLOTS DE CONNEXION
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CLAIMS

What is claimed is:

1. A semiconductor package, comprising:

a die stack including a first active die mounted on a second active die, wherein the first active die includes a bonding pad on a top surface;

an interconnect wire having a first end attached to the bonding pad, wherein the interconnect wire is an only wire attached to the bonding pad; and

a molding compound around the die stack and the interconnect wire, wherein the molding compound covers all of the top surface.

2. The semiconductor package of claim 1, wherein the first active die includes a first type of integrated circuit, and wherein the second active die includes a second type of integrated circuit.

3. The semiconductor package of claim 2, wherein the first active die includes a first silicon grade, and wherein the second active die includes a second silicon grade different than the first silicon grade.

4. The semiconductor package of claim 3, wherein the first active die is a processor die, and wherein the second active die is a memory die.

5. The semiconductor package of claim 1, wherein the molding compound includes an exposed surface vertically above the top surface, and further comprising a solder ball mounted on the exposed surface, wherein the interconnect wire has a second end electrically connected to the solder ball.

6. The semiconductor package of claim 5, wherein the semiconductor package does not include a passive wire carrier between the top surface and the exposed surface.

7. The semiconductor package of claim 1, wherein the first active die includes a first plurality of bonding pads along a first lateral edge of the top surface, wherein the second active die has a second top surface and includes a second plurality of bonding pads along a second lateral edge of the second top surface, and wherein the second plurality of bonding pads are laterally between the first lateral edge and the second lateral edge.

8. The semiconductor package of claim 7, wherein the first plurality of bonding pads has a different number of bonding pads than the second plurality of bonding pads.

9. A semiconductor package assembly, comprising:

a printed circuit board; and

a semiconductor package mounted on the printed circuit board, the semiconductor package including:

a first active die including a bonding pad on a top surface, a second active die under the first active die,

an interconnect wire having a first end attached to the bonding pad, wherein the interconnect wire is an only wire attached to the bonding pad, and

a molding compound surrounding the first active die, the second active die, and the interconnect wire, wherein the molding compound covers all of the top surface.

10. The semiconductor package assembly of claim 9, wherein the first active die is a first type of integrated circuit, and wherein the second active die is a second type of integrated circuit.

11. The semiconductor package assembly of claim 10, wherein the first active die includes a first silicon grade, and wherein the second active die includes a second silicon grade different than the first silicon grade.

12. The semiconductor package assembly of claim 9, wherein the printed circuit board includes a contact pad, wherein the molding compound includes an exposed surface vertically above the top surface, and further comprising a solder ball between the exposed surface and the contact pad, wherein the interconnect wire has a second end electrically connected to the contact pad through the solder ball.

13. The semiconductor package assembly of claim 12, wherein the semiconductor package does not include a passive die between the top surface and the exposed surface.

14. The semiconductor package assembly of claim 9, wherein the first active die includes a first plurality of bonding pads, wherein the second active die includes a second plurality of bonding pads, and wherein the first plurality of bonding pads has a different number of bonding pads than the second plurality of bonding pads.

15. A method, comprising:

mounting a first die stack on a carrier substrate, wherein the first die stack includes a first active die mounted on a second active die, wherein the first active die includes a first bonding pad, and wherein the second active die includes a second bonding pad;

mounting a second die stack on the carrier substrate, wherein the second die stack includes a third active die mounted on a fourth active die, wherein the third active die includes a third bonding pad, and wherein the fourth active die includes a fourth bonding pad;

bonding a plurality of interconnect wires to the die stacks, wherein a first interconnect wire extends between the first bonding pad and the third bonding pad, and wherein a second interconnect wire extends between the second bonding pad and the fourth bonding pad; and

depositing a molding compound over the first die stack, the second die stack, and the interconnect wires, wherein the molding compound fills a medial region between the first die stack and the second die stack.

16. The method of claim 15 further comprising:

removing a portion of the molding compound over the die stacks, and a portion of the interconnect wires within the medial region such that the molding compound includes an exposed surface vertically above the die stacks and the interconnect wires include respective wire segments extending vertically from respective bonding pads to the exposed surface.

17. The method of claim 16 further comprising:

cutting through the molding compound in the medial region to form a first semiconductor package having the first die stack and a second semiconductor package having the second die stack.

18. The method of claim 17 further comprising:

depositing a solder ball on the exposed surface, wherein a first wire segment of the first interconnect wire electrically connects the first bonding pad to the solder ball; and

attaching the solder ball to a contact pad of a printed circuit board.

19. The method of claim 15, wherein a first lateral distance between the first bonding pad and the third bonding pad is greater than a second lateral distance between the second bonding pad and the fourth bonding pad.

20. The method of claim 19, wherein the plurality of interconnect wires are aligned within a vertical plane extending through the bonding pads.