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1. (WO2018063302) REMPLACEMENT DE SOURCE/DRAIN ARRIÈRE POUR DISPOSITIFS À SEMI-CONDUCTEUR À MÉTALLISATION DES DEUX CÔTÉS
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CLAIMS

What is claimed is:

1. An integrated circuit (IC) comprising:

a substrate;

a transistor above the substrate and including:

a gate;

a channel above the gate;

source and drain (S/D) regions adjacent to the channel;

contacts above the S/D regions; and

a seed layer below the S/D regions, wherein the seed layer includes semiconductor material and has doping levels of at least 1E19 atoms per cubic centimeter (cm) less than doping levels of the S/D regions;

at least one metallization layer below the transistor and between the transistor and the substrate; and

at least one metallization layer above the transistor.

2. The IC of claim 1, wherein the channel includes a layer of single-crystal semiconductor material having less than 1E8 dislocation defects per square cm.

3. The IC of claim 1, wherein the channel includes at least one of group IV semiconductor material and group III-V semiconductor material.

4. The IC of claim 1, wherein the transistor further includes a gate dielectric layer between the gate and the channel.

5. The IC of claim 1, wherein the S/D regions each include one of n-type and p-type dopants.

6. The IC of claim 1, wherein the S/D regions include semiconductor material having doping levels of greater than 1E20 atoms per cubic cm.

7. The IC of claim 1, wherein the contacts include one of a metal and a metal alloy material.

8. The IC of claim 1, wherein the seed layer includes at least one of group IV semiconductor material and group III-V semiconductor material.

9. The IC of claim 1, wherein the seed layer includes composite material included in the S/D regions, but with greater concentration of at least one constituent of the composite material.

10. The IC of claim 1, wherein the S/D regions and the seed layer both include silicon germanium (SiGe), and wherein the seed layer includes at least 10 percent less germanium concentration than germanium concentration in the S/D regions.

11. The IC of claim 1, wherein the seed layer includes carbon alloying of at least 1 percent.

12. The IC of claim 1, wherein the seed layer is undoped.

13. The IC of claim 1, wherein the S/D regions include additional contacts below the S/D regions, such that the seed layer is between the additional contacts and the S/D regions and such that the S/D regions are contacted from two or more sides.

14. The IC of claim 1, wherein the transistor includes one of a planar configuration, a finned configuration, and a nanowire configuration.

15. The IC of claim 1, wherein the transistor is one of a p-channel metal-oxide-semiconductor field-effect transistor (p-MOS), an n-channel metal-oxide-semiconductor field-effect transistor (n-MOS), a p-channel tunnel field-effect transistor (p-TFET), and an n-channel tunnel field-effect transistor (n-TFET).

16. A complementary metal-oxide-semiconductor (CMOS) device comprising the IC of any of claims 1-15.

17. A computing system comprising the IC of any of claims 1-15.

18. An integrated circuit (IC) comprising:

a substrate;

a transistor above the substrate and including:

a gate;

a channel above the gate;

source and drain (S/D) regions adjacent to the channel, wherein the S/D regions include semiconductor material and have doping levels above 1E19 atoms per cubic centimeter (cm);

contacts above the S/D regions; and

a seed layer below the S/D regions, wherein the seed layer includes semiconductor material and has doping levels of less than 1E19 atoms per cubic cm;

at least one metallization layer below the transistor and between the transistor and the substrate; and

at least one metallization layer above the transistor.

19. The IC of claim 18, wherein the seed layer includes at least one of group IV semiconductor material and group III-V semiconductor material.

20. The IC of claim 18, wherein the seed layer includes composite material included in the S/D regions, but with greater concentration of at least one constituent of the composite material.

21. The IC of claim 18, wherein the S/D regions and the seed layer both include silicon germanium (SiGe), and wherein the seed layer includes at least 10 percent less germanium concentration than germanium concentration in the S/D regions.

22. The IC of any of claims 18-21, wherein the seed layer includes carbon alloying of at least 1 percent.

23. A method of forming an integrated circuit, the method comprising:

providing a first substrate;

depositing a sacrificial layer on the first substrate;

forming a single-crystal semiconductor material layer on the sacrificial layer;

forming a transistor device using the semiconductor material layer, the transistor including a gate, a channel below the gate, source and drain (S/D) regions adjacent to the channel, and a seed layer above the S/D regions, wherein the S/D regions include sacrificial S/D material;

bonding a metallization layer of the first transistor to a metallization layer of a second substrate;

removing the sacrificial layer to remove the first substrate;

forming contact trenches to access a side of the S/D regions opposite the second substrate;

selectively etching the sacrificial S/D material without completely removing the seed layer to form S/D trenches;

forming final S/D material on the seed layer and in the S/D trenches; and

forming contacts in the contact trenches.

24. The method of claim 23, wherein selectively etching the sacrificial S/D material includes using a given etchant that removes the sacrificial S/D material at least 5 times faster than the given etchant removes material of the seed layer.

25. The method of any of claims 23-24, wherein the seed layer includes at least 1E18 atoms per cubic centimeter (cm) less dopants than the sacrificial S/D material.