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1. (WO2017172195) PROCÉDÉ, APPAREIL ET SYSTÈME POUR UN MÉCANISME DE MODULE D'EXTENSION DE BUS D'EXTENSION D'ORDINATEUR
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CLAIMS

What is claimed is:

1. An apparatus comprising:

a processor;

a bus operably coupled to the processor;

an extension bus slot operably coupled to the bus; and

a circuitry to detect a hot-plug event when inserting or removing a device from the extension bus slot, and to generate a hot-plug message to notify of an occurrence of the hot-plug event, the circuitry comprising:

a state machine to detect the hot-plug event; and

a register to provide at least two bits to mask at least two states of the state machine.

2. The apparatus of claim 1, wherein the register is to select between an in-band hot-plug detection and an out-of-band hot-plug detection.

3. The apparatus of claim 1, wherein the register is to select both an in-band hot-plug detection and an out-of-band hot-plug detection.

4. The apparatus of any one of claims 1-3, wherein the extension bus slot comprises a Peripheral Component Interconnect express (PCIe) slot.

5. The apparatus of any one of claims 1-3, wherein the device comprises a Peripheral Component Interconnect express (PCIe) device.

6. The apparatus of any one of claims 1-3, wherein the state machine comprises a Peripheral Component Interconnect express (PCIe) link training and status state machine (LTSSM), the PCIe LTSSM is to be in at least one of a Detect state, a Polling state or a Configuration state.

7. The apparatus of claim 6, wherein the register is to mask a Polling state indication and a Configuration state indication of the PCIe LTSSM.

8. The apparatus of any one of claims 1-3 comprising:

a virtual port pin (VPP) logic to provide an out of band hot-plug event detection indication.

9. A method comprising:

selecting between an in-band hot-plug detection mechanism, an out-of-band hot-plug detection mechanism, or both the in-band hot-plug detection and the out-of-band hot-plug detection;

detecting a hot-plug event when inserting or removing a device from an extension bus slot, wherein according to the in-band hot-plug detection mechanism, detecting the hot-plug event is by a state machine having at least three states and by masking at least two states of the state machine; and

generating a hot-plug event message to notify of an occurrence of the hot-plug event.

10. The method of claim 9, wherein the extension bus slot comprises a Peripheral Component Interconnect express (PCIe) slot.

11. The method of claim 9, wherein the device comprises a Peripheral Component Interconnect express (PCIe) device.

12. The method of any one of claims 9-11, wherein the state machine comprises a Peripheral Component Interconnect express (PCIe) link training and status state machine (LTSSM), the PCIe LTSSM is to be in at least one of a Detect state, a Polling state or a Configuration state.

13. The method of claim 12, wherein masking comprises:

masking a Polling state indication or a Configuration state indication of the PCIe LTSSM.

14. The method of any one of claims 9-11, wherein according to the out-of-band detection mechanism, detecting the hot-plug event is by a virtual port pin (VPP) logic and by writing a detection of a hot-plug event status into a register.

15. A non-transitory storage medium having stored thereon instructions that, when executed by a machine, result in:

selecting between an in-band hot-plug detection mechanism, an out-of-band hot-plug detection mechanism, or both the in-band hot-plug detection and the out-of-band hot-plug detection;

detecting a hot-plug event when inserting or removing a device from an extension bus slot, wherein according to the in-band hot-plug detection mechanism, detecting the hot-plug event is by a state machine having at least three states and by masking at least two states of the state machine; and

generating a hot-plug event message to notify of an occurrence of the hot-plug event.

16. The non-transitory storage medium of claim 15, wherein the extension bus slot comprises a Peripheral Component Interconnect express (PCIe) slot.

17. The non-transitory storage medium of claim 15, wherein the device comprises a Peripheral Component Interconnect express (PCIe) device.

18. The non-transitory storage medium of any one of claims 15-17, wherein the state machine comprises a Peripheral Component Interconnect express (PCIe) link training and status state machine (LTSSM), the PCIe LTSSM is to be in at least one of a Detect state, a Polling state or a Configuration state.

19. The non-transitory storage medium of claim 18, wherein masking comprises: masking a Polling state indication or a Configuration state indication of the

PCIe LTSSM.

20. The non-transitory storage medium of any one of claims 15-17, wherein according to the out-of-band detection mechanism, detecting the hot-plug event is by a virtual port pin (VPP) logic and by writing a detection of a hot-plug event status into a register.

21. A motherboard comprising:

a processor;

a plurality of buses operably coupled to the processor;

a plurality of extension bus slots operably coupled to the plurality of buses; and

a circuitry to detect a hot-plug event when inserting or removing a device from an extension bus slot of the plurality of extension bus slots, and to generate a hot-plug message to notify of an occurrence of the hot-plug event, the circuitry comprising:

a state machine to detect the hot-plug event; and

a register to provide at least two bits to mask at least two states of the state machine.

22. The motherboard of claim 21, wherein the register is to select between an in-band hot-plug detection and an out-of-band hot-plug detection.

23. The motherboard of claim 21, wherein the register is to select both an in-band hot-plug detection and an out-of-band hot-plug detection.

24. The motherboard of any one of claims 21-23, wherein the state machine comprises a Peripheral Component Interconnect express (PCIe) link training and status state machine (LTSSM), the PCIe LTSSM is to be in at least one of a Detect state, a Polling state or a Configuration state.

25. The motherboard of claim 24, wherein the register is to mask a Polling state indication and a Configuration state indication of the PCIe LTSSM.