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1. (WO2017052558) TECHNIQUES D’EXPOSITION D’UN CÔTÉ ARRIÈRE D’UN DISPOSITIF À CIRCUIT INTÉGRÉ, ET CONFIGURATIONS ASSOCIÉES
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

Claims

What is claimed is:

1 . A method for revealing a backside of an integrated circuit device, the method comprising:

removing a portion of a semiconductor substrate that is coupled to a backside of an integrated circuit (IC) device to leave a remaining portion of the semiconductor substrate coupled to the backside of the IC device; and

removing, by chemical mechanical planarization (CMP) using a selective slurry, the remaining portion of the semiconductor substrate to expose the backside of the IC device.

2. The method of claim 1 , wherein removing the portion of the semiconductor substrate includes:

removing a first portion of the semiconductor substrate by mechanical grinding; and

removing a second portion of the semiconductor substrate by wet etch.

3. The method of claim 1 , wherein the portion of the semiconductor substrate is removed by CMP, grinding, or wet etch.

4. The method of claim 1 , further comprising generating one or more vias in the backside of the IC device to provide access to one or more layers of the IC device.

5. The method of claim 1 , wherein the backside of the IC device includes an isolation oxide.

6. The method of claim 5, wherein the semiconductor substrate is silicon, and wherein the selective slurry is selective for silicon compared with the isolation oxide.

7. The method of claim 5, wherein the isolation oxide is an insulator layer of a silicon-on-insulator (SOI) wafer.

8. The method of any one of claims 1 to 6, wherein the IC device further includes a plurality of semiconductor fins extending into the IC device from the backside of the device.

9. The method of claim 8, further comprising recessing the semiconductor fins from the backside of the device by etching the semiconductor fins.

10. The method of claim 1 , wherein the removing the portion and the removing the remaining portion are performed on a wafer that includes the semiconductor substrate coupled to a plurality of IC devices including the IC device, and wherein the method further comprises bonding a top side of the IC device, opposite the backside, to a carrier wafer prior to the removing the portion and the removing the remaining portion.

1 1 . The method of claim 1 , wherein the removing the remaining portion of the semiconductor substrate by CMP further includes removing a portion of a semiconductor fin of the IC device on the backside of the IC device such that the semiconductor fin has a recessed surface relative to the backside of the IC device.

12. An integrated circuit comprising:

an isolation oxide including a surface that defines a backside of the integrated circuit, wherein the surface of the isolation oxide is not bonded to a semiconductor substrate;

a plurality of semiconductor regions extending from the backside of the integrated circuit into a body of the integrated circuit, wherein the plurality of semiconductor regions are formed of a semiconductor material; and

one or more transistor layers coupled to one or more semiconductor regions of the plurality of semiconductor regions to form one or more transistors.

13. The integrated circuit of claim 12, further comprising one or more vias disposed in the isolation oxide and extending into the body of the integrated circuit from the backside of the integrated circuit.

14. The integrated circuit of claim 13, further comprising:

a top side opposite the backside; and

a plurality of vias extending into the body of the integrated circuit from the top side of the integrated circuit.

15. The integrated circuit of claim 13, further comprising an interconnect layer coupled to the backside of the integrated circuit to route signals to or from the vias.

16. The integrated circuit of any one of claims 12 to 15, wherein the

semiconductor regions are semiconductor fins and the one or more transistors are fin field-effect transistors (finFETs).

17. The integrated circuit of claim 16, wherein the semiconductor fins are recessed from the surface of the isolation oxide on the backside of the integrated circuit.

18. The integrated circuit of any one of claims 12 to 15, wherein the isolation oxide forms shallow trench isolations (STIs), and the semiconductor regions are doped semiconductor wells.

19. A computing device comprising:

a circuit board; and

a die coupled with the circuit board on a front side of the die, the die including:

a plurality of fins extending from a backside of the die into a device layer of the die, wherein the plurality of fins are formed of a semiconductor material, and wherein the backside of the die does not include a semiconductor substrate on the backside that connects the fins;

one or more transistor layers disposed in the device layer and coupled to one or more fins of the plurality of fins to form one or more transistors; and

one or more backside vias extending to the device layer of the die from the backside of the die.

20. The computing device of claim 19, wherein the die is a first die, and wherein the computing device further comprises a second die coupled to the one or more backside vias of the first die.

21 . The computing device of claim 19, wherein the die further includes an isolation oxide disposed between fins of the plurality of fins on the backside of the die.

22. The computing device of claim 19, wherein the die further includes:

a plurality of top side vias extending to the device layer of the die from the top side of the die.

23. The computing device of claim 19, wherein the plurality of fins have a dished surface at or near the backside of the integrated circuit.

24. The computing device of claim 19, wherein the semiconductor material includes silicon.

25. The computing device of any one of claims 19 to 24, wherein:

the die is a processor; and

the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera.