Certains contenus de cette application ne sont pas disponibles pour le moment.
Si cette situation persiste, veuillez nous contacter àObservations et contact
1. (WO2017003959) TECHNIQUES DE LOCALISATION DE FILAMENTS, RÉDUCTION DE L'EFFET DE BORD, ET RÉDUCTION DE LA TENSION D'ÉCRITURE/COMMUTATION DANS LES DISPOSITIFS RRAM
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

Claims

1. A resistive random access memory device, comprising:

a substrate;

a first electrode disposed over the substrate;

a second electrode disposed over the first electrode; and

a resistive random access memory oxide layer disposed between the first electrode and the second electrode;

wherein the resistive random access memory oxide layer has a recess at the interface between the second electrode and the resistive random access memory oxide layer.

2. The resistive random access memory device of claim 1 further comprising an interlayer dielectric disposed on a perimeter of the first electrode, second electrode, and resistive random access memory oxide layer.

3. The resistive random access memory device of claim 1 further comprising an oxygen exchange layer disposed between the resistive random access memory oxide layer and the first electrode.

4. The resistive random access memory device of claim 1, wherein at least one of the cross-section of the recess is v-shaped or square-shaped.

5. The resistive random access memory device of claim 1, wherein at least one of the first electrode or the second electrode comprises titanium nitride.

6. The resistive random access memory device of claim 1, wherein at least a portion of the second electrode is disposed within the recess.

7. A resistive random access memory device, comprising:

a first electrode;

a resistive random access memory oxide layer disposed over the first electrode;

an oxide layer disposed over the resistive random access memory oxide layer;

wherein the oxide layer has a recess region at a center portion extending to a top portion of the resistive random access memory oxide layer; and

a second electrode disposed over the oxide layer.

8. The resistive random access memory device of claim 7, wherein the cross-section of the recess is v-shaped or square-shaped.

9. The resistive random access memory device of claim 7 further comprising an oxygen exchange layer disposed on top of the oxide layer and within the recess region.

10. The resistive random access memory device of claim 7 further comprising a metal layer disposed between the first electrode and the resistive random access memory layer.

11. The resistive random access memory device of claim 10, wherein the metal layer comprises silver or copper.

12. The resistive random access memory device of claim 7, wherein the resistive random access memory oxide layer is disposed on the first electrode.

13. The resistive random access memory device of claim 7, wherein the oxide layer is disposed on the resistive random access memory oxide layer.

14. The resistive random access memory device of claim 7, wherein the recess region has a first recess and a second recess.

15. The resistive random access memory device of claim 14, wherein the first recess has a greater area than the area of the second recess.

16. A method for forming a resistive random access memory device, comprising:

forming a first electrode over a substrate;

forming a dielectric region on lateral portions of the first electrode;

forming a resistive random access memory layer over the first electrode and the dielectric regions;

forming a recess region in the resistive random access memory oxide layer;

forming a second electrode over the resistive random access memory oxide layer wherein a portion of the second electrode fills the recess region;

patterning the second electrode and the resistive random access memory oxide layer to expose the dielectric region on the lateral portions of the first electrode; and

extending the dielectric region on the lateral portions of the first electrode to cover lateral portions of the resistive random access memory oxide layer and the second electrode.

17. The method of claim 16, wherein forming the recess region includes forming a first recess having a first area and forming a second recess having a second area wherein the first area is less than the second area.

18. The method of claim 17, wherein forming the recess region includes:

forming a hardmask layer on the resistive random access memory oxide layer;

forming an opening in the hardmask layer;

forming a spacer material within the opening; and

etching the recess region into the top center portion of resistive random access memory oxide layer;

wherein etching the recess region forms the first recess.

19. The method of claim 18 further comprising etching a second recess within the recess region.

20. The method of claim 16 further comprising forming an oxygen exchange layer on the first electrode wherein the oxygen exchange layer is disposed between the first electrode and the resistive random access memory oxide layer.

21. The method of claim 16 further comprising forming a metal layer on the first electrode; wherein the metal layer is disposed between the first electrode and the resistive random access memory oxide.

22. A computing device, comprising:

a motherboard;

a processor mounted on the motherboard; and

a communication chip fabricated on the same chip as the processor or mounted on the motherboard;

wherein the processor comprises:

a substrate;

a first electrode disposed over the substrate;

a second electrode disposed over the first electrode; and

a resistive random access memory oxide layer disposed between the first electrode and the second electrode;

wherein the resistive random access memory oxide layer has a recess at the interface between the second electrode and the resistive random access memory oxide layer.

23. The computing device of claim 22, wherein at least one of the cross-section of the recess is v-shaped or square-shaped.

24. The computing device of claim 22 further comprising an oxygen exchange layer disposed between the resistive random access memory oxide layer and the first electrode.

25. The computing device of claim 22, wherein at least a portion of the second electrode is disposed within the recess.