Certains contenus de cette application ne sont pas disponibles pour le moment.
Si cette situation persiste, veuillez nous contacter àObservations et contact
1. (WO2016135500) CIRCUITS DE DÉTECTION D'ERREURS DESTINÉS À ÊTRE UTILISÉS AVEC UNE MÉMOIRE
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

What Is Claimed Is:

1 . An integrated circuit, comprising:

a memory array having a plurality of rows of memory cells, wherein a respective row is configured to store a data word and one or more check bits corresponding to the data word;

inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row; and

error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

2. The integrated circuit of claim 1 , wherein the inline error detection circuitry is configured to detect the one or more bit errors in the data word in substantially near realtime based on the one or more check bits.

3. The integrated circuit of claim 1 , wherein the one or more check bits comprise one or more parity bits, and wherein the one or more parity bits are generated using the data word prior to the data word being written to the respective row.

4. The integrated circuit of claim 3, wherein the inline error detection circuitry comprises inline parity checking circuitry, and wherein the inline parity checking circuitry comprises one or more exclusive-OR (XOR) gates, one or more exclusive-NOR (XNOR) gates, or combinations thereof.

5. The integrated circuit of claim 3, further comprising error-correcting code (ECC) bit generation circuitry configured to generate a plurality of first ECC bits based on the data word prior to the data word being written to the respective row.

6. The integrated circuit of claim 5, wherein the first ECC bits are written to an ECC array disposed separately from the memory array.

7. The integrated circuit of claim 5, further comprising ECC detection circuitry, wherein, based on the one or more generated flag bit values indicating the one or more bit errors in the data word, the ECC detection circuitry is configured to:

receive the data word from the respective row;

receive the first ECC bits corresponding to the data word;

generate a plurality of second ECC bits based on the data word received from the respective row;

compare the first ECC bits to the second ECC bits;

determine a position of the one or more bit errors in the data word based on the comparison; and

transmit the position of the one or more bit errors to the error correction circuitry.

8. The integrated circuit of claim 7, wherein the error correction circuitry comprises ECC correction circuitry, and wherein the ECC correction circuitry is configured to:

receive the data word from the respective row;

correct the one or more bit errors in the data word based on the position of the bit error; and

transmit the corrected data word to the memory array for a write operation.

9. The integrated circuit of claim 1 , wherein the one or more check bits comprises a plurality of first error-correcting code (ECC) bits, and further comprising ECC bit generation circuitry configured to generate a plurality of first ECC bits using the data word prior to the data word being written to the respective row.

10. The integrated circuit of claim 9, wherein the inline error detection circuitry comprises ECC detection circuitry, wherein the ECC detection circuitry is configured to: generate a plurality of second ECC bits based on the data word stored in the respective row;

compare the first ECC bits to the second ECC bits;

determine a position of the one or more bit errors in the data word based on the comparison;

generate the one or more flag bit values indicating the one or more bit errors in the data word; and

transmit the position of the one or more bit errors to the error correction circuitry.

1 1 . The integrated circuit of claim 10, wherein the error correction circuitry comprises ECC correction circuitry, and wherein, in response to the one or more generated flag bit values, the ECC correction circuitry is configured to:

receive the data word from the respective row;

correct the one or more bit errors in the data word based on the position of the one or more bit errors; and

transmit the corrected data word to the memory array for a write operation.

12. A method, comprising:

receiving a data word for storage to a row of a memory array;

generating one or more check bits based on the data word;

storing the data word and the one or more check bits to the row;

performing a detection of one or more bit errors in the stored data word using inline error detection circuitry coupled to the row; and

correcting the one or more bit errors in the stored data word using error correction circuitry.

13. The method of claim 12, wherein performing the detection of the one or more bit errors comprises performing the detection using a plurality of exclusive-OR (XOR) gates, one or more exclusive-NOR (XNOR) gates, or combinations thereof.

14. The method of claim 12, wherein generating the one or more check bits comprises generating one or more parity bits using parity bit generation circuitry.

15. The method of claim 14, further comprising generating a plurality of first ECC bits based on the data word prior to the data word being written to the respective row.

16. The method of claim 15, further comprising using ECC detection circuitry upon performing the detection of the one or more bit errors, comprising:

receiving the data word from the respective row;

receiving the first ECC bits corresponding to the data word;

generating a plurality of second ECC bits based on the data word received from the respective row;

comparing the first ECC bits to the second ECC bits;

determining a position of the one or more bit errors in the data word based on the comparison; and

transmitting the position of the one or more bit errors to the error correction circuitry.

17. The method of claim 12, wherein the one or more check bits comprise a plurality of first error-correcting code (ECC) bits.

18. The method of claim 17, wherein performing the detection of the one or more bit errors comprises performing the detection using inline ECC detection circuitry, and further comprising:

generating a plurality of second ECC bits based on the data word stored in the respective row;

comparing the first ECC bits to the second ECC bits;

determining a position of the one or more bit errors in the data word based on the comparison;

generating one or more flag bit values indicating the one or more bit errors in the data word; and

transmitting the position of the one or more bit errors to the error correction circuitry.

19. An integrated circuit, comprising:

a memory array, comprising:

a plurality of rows of memory cells, wherein a respective row is configured to store a horizontal data word and a horizontal parity bit corresponding to the horizontal data word; and

a plurality of columns of memory cells, wherein a respective column is configured to store a vertical data word and a vertical parity bit corresponding to the vertical data word; and

a plurality of error detection circuitry, comprising:

inline horizontal error detection circuitry coupled to the respective row and configured to generate a horizontal flag bit value if the inline horizontal error detection circuitry detects one or more bit errors in the horizontal data word stored in the respective row; and

inline vertical error detection circuitry coupled to the respective column and configured to generate a vertical flag bit if the inline vertical error detection circuitry detects one or more bit errors in the vertical data word stored in the respective column.

20. The integrated circuit of claim 19, wherein the inline horizontal error detection circuitry comprises inline horizontal parity generation circuitry composed of a plurality of horizontal combinational logic gates configured to use the horizontal data word as input; and wherein the inline vertical error detection circuitry comprises inline vertical parity generation circuitry composed of a plurality of vertical combinational logic gates configured to use the vertical data word as input.