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1. (WO2015179606) FOURNITURE D’UNE COMPRESSION DE BANDE PASSANTE DE MÉMOIRE À L’AIDE DE CONTRÔLEURS DE MÉMOIRE COMPRESSÉE (CMC) DANS UN SYSTÈME BASÉ SUR UNE UNITÉ CENTRALE DE TRAITEMENT (CPU)
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

What is claimed is:

1. A compressed memory controller, comprising a memory interface configured to access a system memory via a system bus;

the compressed memory controller configured to:

receive a memory read request comprising a physical address of a memory block to be accessed within a memory line in the system memory;

read a master directory memory block containing a compression indicator (CI) corresponding to the physical address from a master directory in the system memory;

determine, based on the CI, a number of memory blocks within the memory line in the system memory to read for the memory read request; and

read the determined number of memory blocks within the memory line in the system memory beginning at the physical address.

2. The compressed memory controller of claim 1, configured to read the master directory memory block responsive to probabilistically determining that the CI should be read from the master directory;

the compressed memory controller further configured to, responsive to probabilistically determining that the CI should not be read from the master directory, read the CI from one or more error correcting code (ECC) bits associated with the memory block.

3. The compressed memory controller of claim 1, further comprising a CI cache comprising a plurality of CI cache entries each configured to store a previously read master directory memory block;

the compressed memory controller further configured to, prior to reading the master directory memory block, determine whether the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache;

the compressed memory controller configured to read the master directory memory block responsive to determining that the physical address does not correspond to a CI cache entry of the plurality of CI cache entries of the CI cache; and

the compressed memory controller further configured to:

responsive to determining that the physical address does not correspond to a CI cache entry of the plurality CI cache entries of the CI cache:

write the master directory memory block to a CI cache entry of the CI cache; and

read the CI from the CI cache entry of the CI cache; and responsive to determining that the physical address corresponds to the CI cache entry of the plurality CI cache entries of the CI cache, read the CI from the CI cache entry of the CI cache.

4. The compressed memory controller of claim 3, further configured to, prior to writing the master directory memory block to the CI cache entry of the CI cache:

determine whether a current CI cache entry of the CI cache should be evicted; and

responsive to determining that the current CI cache entry should be evicted: determine whether the current CI cache entry has been modified; and responsive to determining that the current CI cache entry has been modified, write the current CI cache entry to the master directory.

5. The compressed memory controller of claim 3, configured to read the master directory memory block further responsive to probabilistically determining that the CI should be read from the master directory;

the compressed memory controller further configured to, responsive to probabilistically determining that the CI should not be read from the master directory, read the CI from one or more error correcting code (ECC) bits associated with the memory block.

6. The compressed memory controller of claim 3, further configured to send an early memory read request to the system memory in parallel with determining whether the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache;

the compressed memory controller configured to read the determined number of memory blocks by being configured to, responsive to determining that the physical address corresponds to the CI cache entry of the plurality CI cache entries of the CI cache, modify the early memory read request based on the CI.

7. The compressed memory controller of claim 3, further configured to perform a cache read operation on a Level 4 (L4) cache in parallel with determining whether the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache.

8. The compressed memory controller of claim 1, configured to determine, based on the CI, the number of memory blocks within the memory line in the system memory to read for the memory read request by being configured to determine a compression pattern indicated by the CI.

9. The compressed memory controller of claim 8, configured to determine the compression pattern indicated by the CI by being configured to determine that the CI comprises a zero-line indicator indicating that zero memory blocks should be read.

10. A compressed memory controller, comprising a memory interface configured to access a system memory via a system bus;

the compressed memory controller configured to:

receive a memory write request comprising write data and a physical address of a memory block to be written within a memory line in the system memory;

determine a compression pattern for the write data;

generate a compression indicator (CI) for the write data based on the compression pattern;

update a stored CI corresponding to the physical address in a master directory with the generated CI;

write the write data to one or more memory blocks in the memory line in the system memory based on the generated CI; and

write the generated CI into one or more error correcting code (ECC) bits of each of the one or more memory blocks in the memory line of the system memory.

11. The compressed memory controller of claim 10, configured to update the stored CI responsive to probabilistically determining that the CI should be updated in the master directory.

12. The compressed memory controller of claim 10, further comprising a CI cache comprising a plurality of CI cache entries each configured to store a previously read master directory memory block;

the compressed memory controller further configured to, prior to updating the stored CI, determine whether the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache;

the compressed memory controller configured to update the stored CI responsive to determining that the physical address does not correspond to a CI cache entry of the plurality of CI cache entries of the CI cache; and the compressed memory controller further configured to:

responsive to determining that the physical address does not correspond to a CI cache entry of the plurality of CI cache entries of the CI cache, write the stored CI to a CI cache entry of the CI cache; and responsive to determining that the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache, update the CI cache entry of the CI cache with the generated CI.

13. The compressed memory controller of claim 12, configured to update the stored CI and write the existing CI to a CI cache entry of the CI cache further responsive to probabilistically determining that the master directory should be updated.

14. The compressed memory controller of claim 12, further configured to, prior to writing the stored CI to the CI cache entry of the CI cache:

determine whether a current CI cache entry of the CI cache should be evicted; and

responsive to determining that the current CI cache entry should be evicted: determine whether the current CI cache entry has been modified; and responsive to determining that the current CI cache entry has been modified, write the CI cache entry to the master directory.

15. A method for providing memory bandwidth compression for memory read requests, comprising:

receiving, by a compressed memory controller via a system bus, a memory read request comprising a physical address of a memory block to be accessed within a memory line in a system memory;

reading a master directory memory block containing a compression indicator

(CI) corresponding to the physical address from a master directory in the system memory;

determining, based on the CI, a number of memory blocks within the memory line in the system memory to read for the memory read request; and reading the determined number of memory blocks within the memory line in the system memory beginning at the physical address.

16. The method of claim 15, wherein reading the master directory memory block is responsive to probabilistically determining that the CI should be read from the master directory;

the method further comprising, responsive to probabilistically determining that the CI should not be read from the master directory, reading the CI from one or more error correcting code (ECC) bits associated with the memory block.

17. The method of claim 15, further comprising:

prior to reading the master directory memory block, determining whether the physical address corresponds to a CI cache entry of a plurality of CI cache entries of a CI cache;

wherein reading the master directory memory block is responsive to determining that the physical address does not correspond to a CI cache entry of the plurality of CI cache entries of the CI cache; and

the method further comprising:

responsive to determining that the physical address does not correspond to a CI cache entry of the plurality CI cache entries of the CI cache:

writing the master directory memory block to a CI cache entry of the CI cache; and

reading the CI from the CI cache entry of the CI cache; and responsive to determining that the physical address corresponds to the CI cache entry of the plurality CI cache entries of the CI cache, reading the CI from the CI cache entry of the CI cache.

18. The method of claim 17, further comprising, prior to writing the master directory memory block to the CI cache entry of the CI cache:

determining whether a current CI cache entry of the CI cache should be evicted; and

responsive to determining that the current CI cache entry should be evicted: determining whether the current CI cache entry has been modified; and responsive to determining that the current CI cache entry has been modified, writing the current CI cache entry to the master directory.

19. The method of claim 17, wherein reading the master directory memory block is further responsive to probabilistically determining that the CI should be read from the master directory;

the method further comprising, responsive to probabilistically determining that the CI should not be read from the master directory, reading the CI from one or more error correcting code (ECC) bits associated with the memory block.

20. The method of claim 17, further comprising sending an early memory read request to the system memory in parallel with determining whether the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache; wherein reading the determined number of memory blocks comprises, responsive to determining that the physical address corresponds to the CI cache entry of the plurality CI cache entries of the CI cache, modifying the early memory read request based on the CI.

21. The method of claim 17, further comprising performing a cache read operation on a Level 4 (L4) cache in parallel with determining whether the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache.

22. The method of claim 15, wherein determining, based on the CI, the number of memory blocks within the memory line in the system memory to read for the memory read request comprises determining a compression pattern indicated by the CI.

23. The method of claim 22, wherein determining the compression pattern indicated by the CI comprises determining that the CI comprises a zero-line indicator indicating that zero memory blocks should be read.

24. A method for providing memory bandwidth compression for memory write requests, comprising:

receiving, by a compressed memory controller via a system bus, a memory write request comprising write data and a physical address of a memory block to be written within a memory line in a system memory; determining a compression pattern for the write data;

generating a compression indicator (CI) for the write data based on the compression pattern;

updating a stored CI corresponding to the physical address in a master directory with the generated CI;

writing the write data to one or more memory blocks in the memory line in the system memory based on the generated CI; and

writing the generated CI into one or more error correcting code (ECC) bits of each of the one or more memory blocks in the memory line of the system memory.

25. The method of claim 24, wherein updating the stored CI is responsive to probabilistically determining that the CI should be updated in the master directory.

26. The method of claim 24, further comprising, prior to updating the stored CI, determining whether a CI corresponding to the physical address exists within a CI cache entry of a plurality of CI cache entries of a CI cache;

wherein updating the stored CI is responsive to determining that a CI corresponding to the physical address does not exist within a CI cache entry of the plurality of CI cache entries of the CI cache; and the method further comprising:

responsive to determining that a CI corresponding to the physical address does not exist within a CI cache entry of the plurality of CI cache entries of the CI cache, writing the stored CI to a CI cache entry of the CI cache; and

responsive to determining that a CI corresponding to the physical address exists within a CI cache entry of the plurality of CI cache entries of the CI cache, updating the CI cache entry of the CI cache with the generated CI.

27. The method of claim 26, wherein updating the stored CI and writing the existing CI to the CI cache entry of the CI cache are further responsive to probabilistically determining that the master directory should be updated.

28. The method of claim 27, further comprising, prior to writing the stored CI to the CI cache entry of the CI cache:

determining whether a current CI cache entry of the CI cache should be evicted; and

responsive to determining that the current CI cache entry should be evicted: determining whether the current CI cache entry has been modified; and responsive to determining that the current CI cache entry has been modified, writing the CI cache entry to the master directory.