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1. WO2013176426 - BOÎTIER DE SEMI-CONDUCTEUR, SON PROCÉDÉ DE FABRICATION, ET BOÎTIER SUR BOÎTIER

Numéro de publication WO/2013/176426
Date de publication 28.11.2013
N° de la demande internationale PCT/KR2013/004073
Date du dépôt international 09.05.2013
CIB
H01L 23/48 2006.1
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
23Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
48Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/538 2006.1
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
23Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
52Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
538la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
CPC
H01L 21/56
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
H01L 21/568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
568Temporary substrate used as encapsulation process aid
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/04105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
H01L 2224/08111
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
081Disposition
08111the bonding area being disposed in a recess of the surface of the body
H01L 2224/08235
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
081Disposition
0812the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
08151the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
08221the body and the item being stacked
08225the item being non-metallic, e.g. insulating substrate with or without metallisation
08235the bonding area connecting to a via metallisation of the item
Déposants
  • 주식회사 네패스 NEPES CO., LTD. [KR]/[KR]
Inventeurs
  • 권용태 KWON, Yong Tae
  • 박경훈 PARK, kyung Hoon
Mandataires
  • 전용준 JEON, Yong Joon
Données relatives à la priorité
10-2012-005634025.05.2012KR
10-2012-005634125.05.2012KR
Langue de publication Coréen (ko)
Langue de dépôt coréen (KO)
États désignés
Titre
(EN) SEMICONDUCTOR PACKAGE, FABRICATION METHOD THEREFOR, AND PACKAGE-ON PACKAGE
(FR) BOÎTIER DE SEMI-CONDUCTEUR, SON PROCÉDÉ DE FABRICATION, ET BOÎTIER SUR BOÎTIER
(KO) 반도체 패키지, 그 제조 방법 및 패키지 온 패키지
Abrégé
(EN) The present invention provides a method for fabricating a semiconductor package including a penetration wire which is precise and has low process defects. The semiconductor package, according to one embodiment of the present invention, comprises: an insulated substrate including a first penetration unit and a second penetration unit; a penetration wire which fills the first penetration unit and is positioned by penetrating the insulated substrate; a semiconductor chip which is positioned within the second penetration unit and is electrically connected to the penetration wire; a molding member for molding the semiconductor chip and the insulated substrate; and a rewiring pattern layer which is positioned on the lower side of the insulated substrate, and which electrically connects the penetration wire and the semiconductor chip.
(FR) La présente invention concerne un procédé de fabrication d'un boîtier de semi-conducteur comportant un câblage de pénétration qui est précis et a peu de défauts durant le processus de fabrication. Le boîtier de semi-conducteur, selon un mode de réalisation de la présente invention, comprend : un substrat isolé comportant une première unité de pénétration et une seconde unité de pénétration; un câblage de pénétration qui remplit la première unité de pénétration et qui est positionné par pénétration du substrat isolé; une puce semi-conductrice qui est positionnée à l'intérieur de la seconde unité de pénétration et qui est électriquement connectée au câblage de pénétration; un élément de moulage servant à mouler la puce semi-conductrice et le substrat isolé; et une couche de motif de recâblage qui est positionnée sur la face inférieure du substrat isolé et qui connecte électriquement le câblage de pénétration et la puce semi-conductrice.
(KO) 본 발명은, 정밀하고 공정 결함이 낮은 관통 배선을 포함하는 반도체 패키지의 제조 방법을 제공한다. 본 발명의 일실시예에 따른 반도체 패키지는, 제1 관통부와 제2 관통부를 포함하는 절연 기판; 상기 제1 관통부를 충전하고, 상기 절연 기판을 관통하여 위치하는 관통 배선; 상기 제2 관통부 내에 위치하고 상기 관통 배선과 전기적으로 연결된 반도체 칩; 상기 반도체 칩과 상기 절연 기판을 몰딩하는 몰딩 부재; 및 상기 절연 기판의 하측에 위치하고, 상기 관통 배선과 상기 반도체 칩을 전기적으로 연결하는 재배선 패턴층을 포함한다.
Documents de brevet associés
DE1120130026724Cette demande ne peut pas être visualisée dans PATENTSCOPE car les données relatives à l'ouverture de la phase nationale n'ont pas encore été publiées ou sont émises par un pays qui ne partage pas de données avec l'OMPI ou il y a un problème de formatage ou d'indisponibilité de la demande.
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