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1. WO2012019867 - PORTE-PUCE, COMPOSANT ÉLECTRONIQUE POURVU D'UN PORTE-PUCE ET PROCÉDÉ DE FABRICATION D'UN PORTE-PUCE

Numéro de publication WO/2012/019867
Date de publication 16.02.2012
N° de la demande internationale PCT/EP2011/062156
Date du dépôt international 15.07.2011
CIB
H01L 23/495 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
23Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
48Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
488formées de structures soudées
495Cadres conducteurs
CPC
H01L 2224/32057
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
3205Shape
32057in side view
H01L 2224/32245
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32245the item being metallic
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48247
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48245the item being metallic
48247connecting the wire to a bond pad of the item
H01L 2224/73265
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73251on different surfaces
73265Layer and wire connectors
H01L 2224/83194
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
83using a layer connector
8319Arrangement of the layer connectors prior to mounting
83194Lateral distribution of the layer connectors
Déposants
  • OSRAM OPTO SEMICONDUCTORS GMBH [DE]/[DE] (AllExceptUS)
  • CHANG, Seng-Teong [MY]/[MY] (UsOnly)
  • OOI, Chee-Eng [MY]/[MY] (UsOnly)
Inventeurs
  • CHANG, Seng-Teong
  • OOI, Chee-Eng
Mandataires
  • EPPING HERMANN FISCHER PATENTANWALTSGESELLSCHAFT MBH
Données relatives à la priorité
10 2010 033 868.010.08.2010DE
Langue de publication allemand (DE)
Langue de dépôt allemand (DE)
États désignés
Titre
(DE) CHIPTRÄGER, ELEKTRONISCHES BAUELEMENT MIT CHIPTRÄGER UND VERFAHREN ZUR HERSTELLUNG EINES CHIPTRÄGERS
(EN) CHIP CARRIER, ELECTRONIC COMPONENT HAVING A CHIP CARRIER, AND METHOD FOR PRODUCING A CHIP CARRIER
(FR) PORTE-PUCE, COMPOSANT ÉLECTRONIQUE POURVU D'UN PORTE-PUCE ET PROCÉDÉ DE FABRICATION D'UN PORTE-PUCE
Abrégé
(DE)
Es wird ein Chipträger (1) angeben, der einen Montagebereich (10) zur Montage eines Halbleiterchips (2) und mindestens einer Vertiefung (12) in einer Oberfläche (11) des Montagebereichs (10) aufweist, wobei die Vertiefung (12) eine laterale Abmessung aufweist, die kleiner als eine laterale Abmessung des Halbleiterchips (2) ist. Weiterhin werden ein elektronisches Bauelement mit einem Chipträger und ein Verfahren zur Herstellung eines Chipträgers angegeben.
(EN)
The invention relates to a chip carrier (1) comprising a mounting region (10) for mounting a semiconductor chip (2) and at least one recess (12) in a surface (11) of the mounting region (10), wherein the recess (12) comprises a lateral dimension smaller than a lateral dimension of the semiconductor chip (2). The invention further relates to an electronic component having a chip carrier and to a method for producing a chip carrier.
(FR)
L'invention concerne un porte-puce (1) qui présente une zone de montage (10) pour le montage d'une puce semi-conductrice (2) et au moins un évidement (12) pratiqué dans une surface (11) de la zone de montage (10), l'évidement (12) présentant une dimension latérale qui est plus petite qu'une dimension latérale de la puce semi-conductrice (2). L'invention concerne également un composant électronique pourvu d'un porte-puce et un procédé de fabrication d'un porte-puce.
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