Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

1. WO2012012369 - ESSAI PARALLÈLE RAPIDE DE MATRICES SRAM

Numéro de publication WO/2012/012369
Date de publication 26.01.2012
N° de la demande internationale PCT/US2011/044440
Date du dépôt international 19.07.2011
CIB
G11C 29/00 2006.01
GPHYSIQUE
11ENREGISTREMENT DE L'INFORMATION
CMÉMOIRES STATIQUES
29Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
CPC
G11C 11/41
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
G11C 2029/1202
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
1202Word line control
G11C 2029/1204
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
1204Bit line control
G11C 2029/2602
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
26Accessing multiple arrays
2602Concurrent test
G11C 29/08
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
G11C 29/28
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
26Accessing multiple arrays
28Dependent multiple arrays, e.g. multi-bit arrays
Déposants
  • ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY [US/US]; 1475 North Scottsdale Road Skysong - Suite 200 Scottsdale, AZ 85257, US (AllExceptUS)
  • CLARK, Lawrence, T. [US/US]; US (UsOnly)
  • CAO, Yu [CN/US]; US (UsOnly)
Inventeurs
  • CLARK, Lawrence, T.; US
  • CAO, Yu; US
Mandataires
  • BEVINS, R., Chad; Withrow & Terranova, P.L.L.C 100 Regency Forest Drive, Suite 160 Cary, NC 27518, US
Données relatives à la priorité
61/365,39619.07.2010US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) FAST PARALLEL TEST OF SRAM ARRAYS
(FR) ESSAI PARALLÈLE RAPIDE DE MATRICES SRAM
Abrégé
(EN)
Systems and methods for performing parallel test operations on Static Random Access Memory (SRAM) cells are disclosed. In general, each parallel test operation is a test operation performed on a block of the SRAM cells in parallel, or simultaneously. In one embodiment, the SRAM cells are arranged into multiple rows and multiple columns where the columns are further arranged into one or more column groups. The block of the SRAM cells for each parallel test operation includes SRAM cells in two or more of the rows, SRAM cells in two or more columns in the same column group, or both SRAM cells in two or more rows and SRAM cells in two or more columns in the same column group.
(FR)
L'invention concerne des systèmes et des procédés qui permettent d'effectuer des opérations d'essai parallèle sur des cellules de mémoire vive statique (SRAM). De manière générale, chaque opération d'essai parallèle est une opération d'essai effectuée sur un bloc des cellules SRAM en parallèle, ou simultanément. Selon un mode de réalisation, les cellules SRAM sont agencées en de multiples rangées et de multiples colonnes, les colonnes étant en outre agencées en un ou plusieurs groupes de colonnes. Le bloc des cellules SRAM pour chaque opération d'essai parallèle comprend des cellules SRAM incluses dans au moins deux rangées, des cellules SRAM incluses dans au moins deux colonnes du même groupe de colonnes, ou à la fois des cellules SRAM incluses dans au moins deux rangées et des cellules SRAM incluses dans au moins deux colonnes du même groupe de colonnes.
Également publié en tant que
Dernières données bibliographiques dont dispose le Bureau international