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1. WO2012009927 - PROCÉDÉ DE PRODUCTION DE STRUCTURE LDMOS SOI À SUPERJONCTION ÉLIMINANT ENTIÈREMENT LE PHÉNOMÈNE DE DÉPLÉTION ASSISTÉE PAR LE SUBSTRAT

Numéro de publication WO/2012/009927
Date de publication 26.01.2012
N° de la demande internationale PCT/CN2010/079822
Date du dépôt international 15.12.2010
CIB
H01L 21/336 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
02Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
04les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
18les dispositifs ayant des corps semi-conducteurs comprenant des éléments du groupe IV de la classification périodique, ou des composés AIIIBV, avec ou sans impuretés, p.ex. des matériaux de dopage
334Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type unipolaire
335Transistors à effet de champ
336à grille isolée
CPC
H01L 21/76283
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
7624using semiconductor on insulator [SOI] technology
76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
76283Lateral isolation by refilling of trenches with dielectric material
H01L 29/0634
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0611for increasing or controlling the breakdown voltage of reverse biased devices
0615by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
063Reduced surface field [RESURF] pn-junction structures
0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
H01L 29/423
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
H01L 29/66659
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66568Lateral single gate silicon transistors
66659with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
H01L 29/66681
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
66681Lateral DMOS transistors, i.e. LDMOS transistors
H01L 29/7824
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
7816Lateral DMOS transistors, i.e. LDMOS transistors
7824with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
Déposants
  • 中国科学院上海微系统与信息技术研究所 SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES [CN/CN]; 中国上海市长宁区长宁路865号 No.865, Changning Road Changning District Shanghai 200050, CN (AllExceptUS)
  • 程新红 CHENG, Xinhong [CN/CN]; CN (UsOnly)
  • 何大伟 HE, Dawei [CN/CN]; CN (UsOnly)
  • 王中健 WANG, Zhongjian [CN/CN]; CN (UsOnly)
  • 徐大伟 XU, Dawei [CN/CN]; CN (UsOnly)
  • 夏超 XIA, Chao [CN/CN]; CN (UsOnly)
  • 宋朝瑞 SONG, Zhaorui [CN/CN]; CN (UsOnly)
  • 俞跃辉 YU, Yuehui [CN/CN]; CN (UsOnly)
Inventeurs
  • 程新红 CHENG, Xinhong; CN
  • 何大伟 HE, Dawei; CN
  • 王中健 WANG, Zhongjian; CN
  • 徐大伟 XU, Dawei; CN
  • 夏超 XIA, Chao; CN
  • 宋朝瑞 SONG, Zhaorui; CN
  • 俞跃辉 YU, Yuehui; CN
Mandataires
  • 上海光华专利事务所 J.Z.M.C PATENT AND TRADEMARK LAW OFFICE; 中国上海市杨浦区国定路335号5022室 Room 5022, No.335, GUODing Road YANG Pu District, Shanghai 200433, CN
Données relatives à la priorité
201010231665.520.07.2010CN
Langue de publication chinois (ZH)
Langue de dépôt chinois (ZH)
États désignés
Titre
(EN) PROCESS FOR PRODUCING SOI SUPER JUNCTION LDMOS STRUCTURE COMPLETELY ELIMINATING EFFECT OF SUBSTRATE ASSISTED DEPLETION
(FR) PROCÉDÉ DE PRODUCTION DE STRUCTURE LDMOS SOI À SUPERJONCTION ÉLIMINANT ENTIÈREMENT LE PHÉNOMÈNE DE DÉPLÉTION ASSISTÉE PAR LE SUBSTRAT
(ZH) 可完全消除衬底辅助耗尽效应的SOI超结LDMOS结构的制作工艺
Abrégé
(EN)
A process for producing a silicon on silicon (SOI) super junction lateral double-diffused MOSFET (LDMOS) structure completely eliminating the effect of substrate assisted depletion comprises the following steps: making a conductive layer (10) under a buried oxide layer (9) by using a bonding process; making the super junction LDMOS structure on the SOI substrate having the conductive layer (10). The detailed production process of the conductive layer (10) comprises: depositing a barrier layer on the first bulk silicon wafer, and then depositing a charge guide layer to obtain the first intermediate structure; thermally oxidating the second bulk silicon wafer to form a silicon oxide layer, and then depositing a barrier layer, and finally depositing a charge guide layer to obtain the second intermediate structure; bonding the first intermediate structure to the second intermediate structure by a metal bonding technique to form the conductive layer (10) under the SOI buried oxide layer (9). The present invention can release charge accumulated at the low interface of the buried oxide layer (9) and eliminate influence of the longitudinal electric field on charge balance of a p/n pillar area, to completely eliminate the effect of substrate assisted depletion and improve the breakdown voltage of device.
(FR)
Cette invention concerne un procédé de production d'une structure MOSFET silicium sur isolant (SOI) à superjonction à double diffusion latérale (LDMOS) qui élimine entièrement le phénomène de déplétion assistée par le substrat. Ledit procédé comprend les étapes consistant à : former une couche conductrice (10) sous une couche d'oxyde enterrée (9) en utilisant un procédé de liaison ; former la structure LDMOS à superjonction sur le substrat qui comprend la couche conductrice (10). Le procédé de production de production de la couche conductrice (10) comprend plus particulièrement les étapes consistant à : déposer une couche barrière sur la première tranche massive de silicium, et déposer ensuite une couche guide de charge pour obtenir la première structure intermédiaire ; oxyder par oxydation thermique la seconde tranche massive de silicium pour former une couche d'oxyde de silicium, déposer ensuite une couche barrière, et déposer enfin une couche guide de charge pour obtenir une seconde structure intermédiaire ; relier la première structure intermédiaire à la seconde structure intermédiaire par une technique de liaison par apport de métal pour former la couche conductrice (10) en dessous de la couche d'oxyde enterrée (9) de la structure SOI. Le procédé selon l'invention permet de libérer la charge accumulée à l'interface inférieure de la couche d'oxyde enterrée (9), et d'éliminer l'influence du champ électrique longitudinal sur l'équilibre de charge d'une région de pilier de type p/n, de sorte à éliminer entièrement le phénomène de déplétion assistée par le substrat et à améliorer la tension de claquage du dispositif.
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