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1. WO2012006766 - STRUCTURE SEMICONDUCTRICE ET PROCÉDÉ DE FABRICATION DE CELLE-CI

Numéro de publication WO/2012/006766
Date de publication 19.01.2012
N° de la demande internationale PCT/CN2010/001498
Date du dépôt international 27.09.2010
CIB
H01L 21/768 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
70Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ci; Fabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
71Fabrication de parties spécifiques de dispositifs définis en H01L21/7089
768Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
23Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
52Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
522comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
528Configuration de la structure d'interconnexion
CPC
H01L 21/76804
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76804by forming tapered via holes
H01L 21/76811
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76811involving multiple stacked pre-patterned masks
H01L 21/76813
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76813involving a partial via etch
H01L 21/76832
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76829characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
76832Multiple layers
H01L 21/76834
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76829characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
76834formation of thin insulating films on the sidewalls or on top of conductors
H01L 23/5329
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
5329Insulating materials
Déposants
  • 中国科学院微电子研究所 INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES [CN/CN]; 中国北京市朝阳区北土城西路3号 No. 3 Beitucheng West Road Chaoyang District Beijing 100029, CN (AllExceptUS)
  • 朱慧珑 ZHU, Huilong [US/US]; US (UsOnly)
  • 尹海洲 YIN, Haizhou [CN/US]; US (UsOnly)
  • 骆志炯 LUO, Zhijiong [CN/US]; US (UsOnly)
Inventeurs
  • 朱慧珑 ZHU, Huilong; US
  • 尹海洲 YIN, Haizhou; US
  • 骆志炯 LUO, Zhijiong; US
Mandataires
  • 中科专利商标代理有限责任公司 CHINA SCIENCE PATENT & TRADEMARK AGENT LTD; 中国北京市海淀区王庄路1号清华同方科技大厦B座25层 25/F., Bldg. B, Tsinghua Tongfang Hi-Tech Plaza No. 1, Wangzhuang Rd. Haidian District Beijing 100083, CN
Données relatives à la priorité
201010232060.814.07.2010CN
Langue de publication chinois (ZH)
Langue de dépôt chinois (ZH)
États désignés
Titre
(EN) SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
(FR) STRUCTURE SEMICONDUCTRICE ET PROCÉDÉ DE FABRICATION DE CELLE-CI
(ZH) 半导体结构及其制造方法
Abrégé
(EN)
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor device comprises a semiconductor substrate (100), a local interconnection structure (120) connected with the semiconductor substrate (100), a laminated structure of through hole (220) electrically connected with the local interconnection structure (120). The laminated structure of through hole (220) comprises a through hole (221), a through hole sidewall (224), an insulating layer (225) and a conductive plug (226), wherein, the through hole (221) includes an upper through hole (222) and a lower through hole (223), the width of the upper through hole (222) is larger than the width of the lower through hole (223); the through hole sidewall (224) is adjacent to the inner wall of the lower through hole (223); the surface of the through hole (221) and the through hole sidewall (224) is covered with the insulating layer (225); the conductive plug (226) is formed in a space enclosed by the insulating layer (225) and is electrically connected with the local interconnection structure (120).
(FR)
L'invention concerne une structure semiconductrice et un procédé de fabrication de celle-ci. Le dispositif semiconducteur comprend un substrat semiconducteur (100), une structure d'interconnexion locale (120) connectée au substrat semiconducteur (100), une structure stratifiée de trous traversants (220) connectés électriquement à la structure d'interconnexion locale (120). La structure stratifiée de trous traversants (220) comprend un trou traversant (221), une paroi latérale de trou traversant (224), une couche d'isolation (225) et un bouchon conducteur (226). Le trou traversant (221) comprend un trou traversant supérieur (222) et un trou traversant inférieur (223). La largeur du trou traversant supérieur (222) est supérieure à celle du trou traversant inférieur (223). La paroi latérale de trou traversant (224) est adjacente à la paroi intérieure du trou traversant inférieur (223). La surface du trou traversant (221) et la paroi latérale de trou traversant (224) sont recouvertes par la couche d'isolation (225). Le bouchon conducteur (226) est formé dans un espace délimité par la couche d'isolation (225) et il est connecté électriquement à la structure d'interconnexion locale (120).
(ZH)
提供了一种半导体结构及其制造方法,该半导体结构包括:半导体衬底(100);局部互连结构(120),与半导体衬底(100)连接;通孔叠层结构(220),与局部互连结构(120)电连接。通孔叠层结构(220)包括过孔(221)、过孔侧墙(224)、绝缘层(225)和导电塞(226)。其中,过孔(221)包括上过孔(222)和下过孔(223),上过孔(222)的宽度大于下过孔(223)的宽度;过孔侧墙(224)紧邻下过孔(223)的内壁;绝缘层(225)覆盖过孔(221)和过孔侧墙(224)的表面;导电塞(226)形成于绝缘层(225)围绕的空间内,并与局部互连结构(120)电连接。
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