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1. WO2011050444 - CARTE DE CIRCUIT IMPRIMÉ À INTERCONNEXIONS DE SOUDURE À TOPOGRAPHIE VARIABLE

Numéro de publication WO/2011/050444
Date de publication 05.05.2011
N° de la demande internationale PCT/CA2010/001473
Date du dépôt international 29.09.2010
CIB
H05K 1/02 2006.01
HÉLECTRICITÉ
05TECHNIQUES ÉLECTRIQUES NON PRÉVUES AILLEURS
KCIRCUITS IMPRIMÉS; ENVELOPPES OU DÉTAILS DE RÉALISATION D'APPAREILS ÉLECTRIQUES; FABRICATION D'ENSEMBLES DE COMPOSANTS ÉLECTRIQUES
1Circuits imprimés
02Détails
H05K 1/16 2006.01
HÉLECTRICITÉ
05TECHNIQUES ÉLECTRIQUES NON PRÉVUES AILLEURS
KCIRCUITS IMPRIMÉS; ENVELOPPES OU DÉTAILS DE RÉALISATION D'APPAREILS ÉLECTRIQUES; FABRICATION D'ENSEMBLES DE COMPOSANTS ÉLECTRIQUES
1Circuits imprimés
16comprenant des composants électriques imprimés incorporés, p.ex. une résistance, un condensateur, une inductance imprimés
H05K 3/00 2006.01
HÉLECTRICITÉ
05TECHNIQUES ÉLECTRIQUES NON PRÉVUES AILLEURS
KCIRCUITS IMPRIMÉS; ENVELOPPES OU DÉTAILS DE RÉALISATION D'APPAREILS ÉLECTRIQUES; FABRICATION D'ENSEMBLES DE COMPOSANTS ÉLECTRIQUES
3Appareils ou procédés pour la fabrication de circuits imprimés
CPC
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/73204
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73201on the same surface
73203Bump and layer connectors
73204the bump connector being embedded into the layer connector
H05K 2201/09136
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
09Shape and layout
09009Substrate related
09136Means for correcting warpage
H05K 2201/094
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
09Shape and layout
09209Shape and layout details of conductors
09372Pads and lands
094Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
H05K 2201/099
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
09Shape and layout
09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
099Coating over pads, e.g. solder resist partly over pads
Déposants
  • ATI TECHNOLOGIES ULC [CA]/[CA] (AllExceptUS)
  • TOPACIO, Roden [CA]/[CA] (UsOnly)
  • LEUNG, Andrew [CA]/[CA] (UsOnly)
Inventeurs
  • TOPACIO, Roden
  • LEUNG, Andrew
Mandataires
  • SMART & BIGGAR
Données relatives à la priorité
12/610,94902.11.2009US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) CIRCUIT BOARD WITH VARIABLE TOPOGRAPHY SOLDER INTERCONNECTS
(FR) CARTE DE CIRCUIT IMPRIMÉ À INTERCONNEXIONS DE SOUDURE À TOPOGRAPHIE VARIABLE
Abrégé
(EN)
Various circuit boards and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a solder mask to a first side of a first circuit board. The first side of the first circuit board includes a first conductor structure and a second conductor structure. A first opening is formed in the solder mask that extends to the first conductor structure. The first opening has a first area. A second opening is formed in the solder mask that extends to the second conductor structure and has a second area larger than the first area.
(FR)
L'invention porte sur diverses cartes de circuit imprimé et leur procédé de fabrication. Selon un aspect, un procédé de fabrication est décrit qui consiste à appliquer un masque de soudure à un premier côté d'une première carte de circuit imprimé. Le premier côté de la première carte de circuit imprimé comprend une première structure conductrice et une seconde structure conductrice. Une première ouverture est formée dans le masque de soudure qui s'étend jusqu'à la première structure conductrice. La première ouverture possède une première aire. Une seconde ouverture est formée dans le masque de soudure qui s'étend jusqu'à la seconde structure conductrice et possède une seconde aire plus grande que la première aire.
Également publié en tant que
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