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1. WO2008099554 - STRUCTURE POUR LE MONTAGE D'UN BOÎTIER DE SEMI-CONDUCTEUR

Numéro de publication WO/2008/099554
Date de publication 21.08.2008
N° de la demande internationale PCT/JP2007/073200
Date du dépôt international 30.11.2007
CIB
H01L 23/40 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
23Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
34Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
40Supports ou moyens de fixation pour les dispositifs de refroidissement ou de chauffage amovibles
CPC
H01L 2224/0554
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
H01L 2224/05568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05568the whole external layer protruding from the surface
H01L 2224/05573
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05573Single external layer
H01L 2224/16
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
H01L 2224/32188
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32153the body and the item being arranged next to each other, e.g. on a common substrate
32175the item being metallic
32188the layer connector connecting to a bonding area protruding from the surface of the item
H01L 23/3677
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation ; ; Temperature sensing arrangements
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
367Cooling facilitated by shape of device
3677Wire-like or pin-like cooling fins or heat sinks
Déposants
  • 日本電気株式会社 NEC CORPORATION [JP]/[JP] (AllExceptUS)
  • 佐々木 純一 SASAKI, Junichi [JP]/[JP] (UsOnly)
  • 樋野 智之 HINO, Tomoyuki [JP]/[JP] (UsOnly)
Inventeurs
  • 佐々木 純一 SASAKI, Junichi
  • 樋野 智之 HINO, Tomoyuki
Mandataires
  • 宮崎 昭夫 MIYAZAKI, Teruo
Données relatives à la priorité
2007-03510115.02.2007JP
Langue de publication japonais (JA)
Langue de dépôt japonais (JA)
États désignés
Titre
(EN) STRUCTURE FOR MOUNTING SEMICONDUCTOR PACKAGE
(FR) STRUCTURE POUR LE MONTAGE D'UN BOÎTIER DE SEMI-CONDUCTEUR
(JA) 半導体パッケージの実装構造
Abrégé
(EN)
In a mounting structure, a semiconductor package (1) and a heat sink (8) for dissipating heat generated from the semiconductor package (1) are mounted on a mounting board (3). The rear surface of the semiconductor package (1) is bonded to the front surface of the mounting board (3) facing the rear surface. The heat sink (8) is brought into contact with the rear surface of the semiconductor package (1) through a through hole (5) formed on the mounting substrate (3). The semiconductor package (1) and the heat sink (8) are pressed to each other by an elastic force of a clip (6).
(FR)
Dans une structure de montage, un boîtier de semi-conducteur (1) et un dissipateur thermique (8) pour dissiper de la chaleur générée à partir du boîtier de semi-conducteur (1) sont montés sur une carte de montage (3). La surface arrière du boîtier de semi-conducteur (1) est liée à la surface avant de la carte de montage (3) opposée à la surface arrière. Le dissipateur thermique (8) est amené en contact avec la surface arrière du boîtier de semi-conducteur (1) par un trou traversant (5) formé sur le substrat de montage (3). Le boîtier de semi-conducteur (1) et le dissipateur thermique (8) sont pressés l'un contre l'autre par une force élastique d'une attache (6).
(JA)
 半導体パッケージ1と、該半導体パッケージ1から発生した熱を放熱するためのヒートシンク8とが実装基板3に搭載された実装構造である。半導体パッケージ1の裏面は該裏面と対向する実装基板3の表面に接合されている。ヒートシンク8、実装基板3に形成された貫通穴5を介して半導体パッケージ1の裏面に接触している。そして、半導体パッケージ1とヒートシンク8とが、クリップ6の弾性力によって互いに相手方に対して押し付けられている。
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