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1. WO2007149655 - FABRICATION DE STRUCTURES DE SILICIUM DE TAILLE INFÉRIEURE AUX LIMITES DE RÉSOLUTION OPTIQUE

Numéro de publication WO/2007/149655
Date de publication 27.12.2007
N° de la demande internationale PCT/US2007/068949
Date du dépôt international 15.05.2007
CIB
H01L 21/44 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
02Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
04les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
34les dispositifs ayant des corps semi-conducteurs non couverts par H01L21/06, H01L21/16 et H01L21/18156
44Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes H01L21/36-H01L21/428177
CPC
H01L 21/28132
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
28008Making conductor-insulator-semiconductor electrodes
28017the insulator being formed after the semiconductor body, the semiconductor being silicon
28026characterised by the conductor
28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
28132conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
H01L 27/11521
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
H01L 27/11524
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
11524with cell select transistors, e.g. NAND
H01L 29/40114
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
401Multistep manufacturing processes
4011for data storage electrodes
40114the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
H01L 29/42328
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42324Gate electrodes for transistors with a floating gate
42328with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
Déposants
  • ATMEL CORPORATION [US/US]; 2325 Orchard Parkway San Jose, CA 95131, US (AllExceptUS)
  • LOJEK, Bohumil [US/US]; US (UsOnly)
Inventeurs
  • LOJEK, Bohumil; US
Mandataires
  • STEFFEY, Charles, E. ; Schwegman, Lundberg & Woessner, P.A. P.O. Box 2938 Minneapolis, MN 55402, US
Données relatives à la priorité
11/425,36420.06.2006US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) MANUFACTURING OF SILICON STRUCTURES SMALLER THAN OPTICAL RESOLUTION LIMITS
(FR) FABRICATION DE STRUCTURES DE SILICIUM DE TAILLE INFÉRIEURE AUX LIMITES DE RÉSOLUTION OPTIQUE
Abrégé
(EN)
Method for forming silicon structures, such as upright gates or fins on a wafer substrate, particularly for use as a building block for semiconductor devices. The structures are smaller than can be resolved by conventional optical lithography. A plan of the structure is mapped to a substrate as an ideal. Conductive and insulative layers are deposited onto the substrate and a work region by photolithography. An opening is etched in the work region and a frame is created protective of the desired structure. Mask of the fram is etched away except over the structure and then this portion is used to protect the structure so that remaining material can be removed until only the gate over the substrate remains. This process is carried out in many places over a wafer with the structures preferably aligned in rows and columns for making memory or logic arrays.
(FR)
L'invention concerne un procédé de formation de structures de silicium, telles que des grilles ou bâtonnets verticaux sur un substrat de plaquette, utilisables en particulier comme bloc de construction pour des dispositifs semiconducteurs. Ces structures sont plus petites que les dimensions gérées par la lithographie optique classique. Un plan de la structure est mappé relativement à un substrat en tant que modèle idéal. Des couches conductrices et isolantes sont déposées par photolithographie sur le substrat et sur une zone de travail. Une ouverture est gravée dans la zone de travail et une araignée de connexion est créée qui protège la structure désirée. Un masque de l'araignée de connexion est gravé vers l'extérieur sauf sur la structure, puis cette partie est utilisée pour protéger la structuure de sorte que le matériau restant puisse être éliminé jusqu'à ce qu'il ne reste plus que la grille sur le substrat. Ce procédé est réalisé en maints endroits sur une plaquette dont les structures sont, de préférence, alignées en rangées et en colonnes afin de créer des réseaux mémoire ou logiques.
Dernières données bibliographiques dont dispose le Bureau international