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1. WO2007143130 - STRUCTURE MOSFET HAUTES PERFORMANCES À GRILLE FENDUE PLANE ET SON PROCÉDÉ DE FABRICATION

Numéro de publication WO/2007/143130
Date de publication 13.12.2007
N° de la demande internationale PCT/US2007/013005
Date du dépôt international 30.05.2007
CIB
H01L 29/76 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
29Dispositifs à semi-conducteurs spécialement adaptés au redressement, à l'amplification, à la génération d'oscillations ou à la commutation et ayant au moins une barrière de potentiel ou une barrière de surface; Condensateurs ou résistances ayant au moins une barrière de potentiel ou une barrière de surface, p.ex. jonction PN, région d'appauvrissement, ou région de concentration de porteurs de charges; Détails des corps semi-conducteurs ou de leurs électrodes
66Types de dispositifs semi-conducteurs
68commandables par le seul courant électrique fourni ou par la seule tension appliquée, à une électrode qui ne transporte pas le courant à redresser, amplifier ou commuter
76Dispositifs unipolaires
CPC
H01L 21/26586
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26Bombardment with radiation
263with high-energy radiation
265producing ion implantation
26586characterised by the angle between the ion beam and the crystal planes or the main crystal surface
H01L 29/0847
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
08with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
0843Source or drain regions of field-effect devices
0847of field-effect transistors with insulated gate
H01L 29/0878
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
08with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
0843Source or drain regions of field-effect devices
0847of field-effect transistors with insulated gate
0852of DMOS transistors
0873Drain regions
0878Impurity concentration or distribution
H01L 29/1095
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
10with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
1095Body region, i.e. base region, of DMOS transistors or IGBTs
H01L 29/402
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
402Field plates
H01L 29/41741
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
417carrying the current to be rectified, amplified or switched
41725Source or drain electrodes for field effect devices
41741for vertical or pseudo-vertical devices
Déposants
  • ALPHA & OMEGA SEMICONDUCTOR, LTD. [--/US]; Canon's Court, 22 Victoria Street Hamilton HM12, BM (AllExceptUS)
Inventeurs
  • BHALLA, Anup; US
  • HÉBERT, François; US
  • NG, Daniel, S.; US
Mandataires
  • LIN, Bo-In; 13445 Mandoli Drive Los Altos Hills, CA 94022, US
Données relatives à la priorité
11/444,85331.05.2006US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) PLANAR SPLIT-GATE HIGH-PERFORMANCE MOSFET STRUCTURE AND MANUFACTURING METHOD
(FR) STRUCTURE MOSFET HAUTES PERFORMANCES À GRILLE FENDUE PLANE ET SON PROCÉDÉ DE FABRICATION
Abrégé
(EN)
This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.
(FR)
La présente invention divulgue un dispositif d'alimentation à semi-conducteur amélioré comprenant une pluralité de cellules transistor de puissance, chaque cellule comportant en outre une grille plane rembourrée par une couche d'oxyde de grille disposée au sommet d'une couche de dérive constituant une couche supérieure d'un substrat semi-conducteur, la grille plane constituant de plus une grille fendue comprenant un entrefer ouvert dans une couche de grille au moyen duquel la superficie totale de la grille est réduite. La cellule transistor comporte en outre une région de diffusion JFET (transistor à effet de champ de jonction) disposée dans la couche de dérive sous l'entrefer de la couche de grille, la région de diffusion JFET présentant une concentration de dopant plus élevée que la région de dérive permettant de réduire une résistance de canal du dispositif d'alimentation à semi-conducteur. La cellule transistor comporte en outre une région dopée de surface peu profonde disposée près d'une surface supérieure de la couche de dérive sous la grille adjacente à la région de diffusion JFET, la région dopée de surface peu profonde présentant concentration de dopant inférieure à la région de diffusion JFET et supérieure à la couche de dérive.
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