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1. (WO2007002860) PASSIVATION DE DISPOSITIFS SEMI-CONDUCTEURS À BASE DE LARGE BANDE INTERDITE AVEC NITRURES PULVÉRISÉS SANS HYDROGÈNE
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

Claims
1. A passivated semiconductor structure comprising:
a substrate selected from the group consisting of silicon carbide and the Group III nitrides;
a passivation layer selected from the group consisting of nitrides that are substantially hydrogen free, sputtered nitrides, and non-stoichiometric nitrides; and
an environmental barrier selected from the group consisting of CVD-deposited nitrides and stoichiometric nitrides.

2. A passivated semiconductor structure according to Claim 1 wherein:
said substrate is silicon carbide; and
said passivated semiconductor structure further comprising an oxidation layer on said silicon carbide substrate for lowering the interface density between said silicon carbide substrate and said thermal oxidation layer; and
wherein said passivated layer comprises:
a first sputtered non-stoichiometric silicon nitride layer on said thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping;
a second sputtered non-stoichiometric silicon nitride layer on said first layer for positioning subsequent passivation layers further from said substrate without
encapsulating said structure; and
a sputtered stoichiometric silicon nitride layer on said second sputtered layer for encapsulating said structure and for enhancing the hydrogen barrier properties of the passivation layers.

3. A passivated semiconductor structure according to Claim 2 wherein said thermal oxidation layer is silicon dioxide with a thickness of between about 100 and 500 angstroms.

4. A passivated semiconductor structure according to Claim 2 wherein said first silicon nitride layer is between about 1000 and 2000 angstroms thick.

5. A passivated semiconductor structure according to Claim 2 wherein said first silicon nitride layer has a refractive index of between about 1.85 and 1.95.

6. A passivated semiconductor structure according to Claim 2 wherein said second silicon nitride layer is between about 1000 and 3000 angstroms thick.

7. A passivated semiconductor structure according to Claim 2 wherein said second silicon nitride layer has a refractive index of between about 1.85 and 1.95.

8. A passivated semiconductor structure according to Claim 2 wherein said stoichiometric encapsulating layer is between about 1000 and 3000 angstroms thick.

9. A passivated semiconductor structure according to Claim 2 wherein said environmental barrier layer is between about 2000 and 5000 angstroms.

10. A passivated semiconductor structure according to Claim 2 wherein said environmental barrier layer and said encapsulating layer both comprise Si3N4.

11. A passivated semiconductor structure according to Claim 2 wherein said silicon carbide substrate is a single crystal having a polytype selected from the group consisting of the 3 C, 4H, 6H, and 15Rpolytypes of silicon carbide.

12. A passivated semiconductor structure according to Claim 1 wherein:
said substrate is a Group III nitride layer; and
wherein said passivation layer comprises:
at least one sputtered layer of non-stoichiometric nitride selected from the group consisting of silicon nitride, aluminum nitride, oxynitrides of silicon and oxynitrides of aluminum, and at least one chemical vapor deposited layer of silicon nitride for positioning said passivation layers further from said Group III nitride layer without fully encapsulating said structure.

13. A passivated semiconductor structure according to Claim 12 further comprising a gate contact to said Group III nitride layer.

14. A passivated semiconductor structure according to Claim 13 wherein said Group III nitride layer has a first conductivity type; said structure further comprising:
respective source and drain regions in said Group III nitride layer and having the opposite conductivity type from said remainder of said Group III nitride layer and defining a channel therebetween; and
ohmic contacts to said source and drain regions.

15. A passivated semiconductor structure according to Claim 12 wherein said Group III nitride layer is selected from the group consisting of gallium nitride and aluminum gallium nitride.

16. A passivated semiconductor structure according to Claim 12 wherein said second passivation structure comprises a sputtered stoichiometric layer of silicon nitride and a chemical vapor deposited stoichiometric layer of silicon nitride.

17. A passivated semiconductor structure according to Claim 12 wherein said first passivation structure has a refractive index of between about 1.85 and 1.95.

18. A passivated semiconductor structure according to Claim 12 wherein:
said sputtered layer of non-stoichiometric silicon nitride in said first passivation structure is between about 1000 and 2000 angstroms thick;
said chemical vapor deposited layer of silicon nitride in said the first passivation structure is between about 1000 and 3000 angstroms thick; and
said second passivation structure is between about 3000 and 8000 angstroms thick.

19. An insulated semiconductor device that incorporates the structure of Claim 1, said device comprising:
a silicon carbide substrate having a first conductivity type;
respective source and drain regions in said substrate having the opposite conductivity type and defining a channel therebetween;

a thermal oxide layer on said substrate between said source and drain for lowering the interface density between said silicon carbide substrate and said thermal oxidation layer;
a gate contact on said thermal oxide layer;
a first passivation structure formed of non-stoichiometric silicon nitride on said thermal oxide layer for reducing parasitic capacitance and minimizing device trapping and positioning subsequent passivation layers further from said substrate; and
a second passivation structure formed of stoichiometric silicon nitride on said first passivation structure for providing an environmental barrier for said device.

20. An insulated semiconductor device according to Claim 19 further comprising conductive contacts to said source region and said drain region.

21. An insulated semiconductor device according to Claim 19 wherein said first passivation structure comprises two layers of sputtered non-stoichiometric silicon nitride on said thermal oxide layer.

22. An insulated semiconductor device according to Claim 19 wherein said second passivation structure comprises a sputter-deposited layer of silicon nitride on said first passivation structure and a chemical vapor deposited layer of silicon nitride on said spotter-deposited layer.

23. An insulated semiconductor device according to Claim 19 wherein both of said layers in said second passivation structure comprise Si3N4.

24. An insulated semiconductor device according to Claim 19 wherein said first passivation structure is between about 2000 and 5000 angstroms thick and has a refractive index of between about 1.85 and 1.95.

25. An insulated semiconductor device according to Claim 19 wherein said second passivation structure is between about 3000 and 8000 angstroms thick and has a refractive index of about 2.04.

26. A passivated semiconductor structure according to Claim 1 wherein:
said substrate is silicon carbide; and
wherein said passivation layer comprises:
a thermal oxidation layer on said silicon carbide substrate for lowering the interface density between said silicon carbide substrate and said thermal oxidation layer; a first substantially hydrogen-free non-stoichiometric silicon nitride layer on said thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping;
a second substantially hydrogen-free non-stoichiometric silicon nitride layer on said first layer for positioning subsequent passivation layers further from said substrate without encapsulating said structure; and
a substantially hydrogen-free stoichiometric silicon nitride layer on said second substantially hydrogen-free layer for encapsulating said structure and for enhancing the hydrogen barrier properties of the passivation layers.

27. A passivated semiconductor structure according to Claim 26 wherein said first and second substantially hydrogen free stoichiometric silicon nitride layers are sputter-deposited layers.

28. A passivated semiconductor structure according to Claim 26 wherein said substantially hydrogen free stoichiometric silicon nitride layer comprises a sputtered layer.

29. A passivated semiconductor structure according to Claim 26 wherein said environmental barrier layer of stoichiometric silicon nitride comprises a chemical vapor deposited layer.

30. A passivated structure according to Claim 26 wherein said first silicon nitride layer is between about 1000 and 2000 angstroms thick and has a refractive index of between about 1.85 and 1.95.

31. A passivated structure according to Claim 26 wherein said second silicon nitride layer is between about 1000 and 3000 angstroms thick and has a refractive index of between about 1.85 and 1.95.

32. A passivated semiconductor structure according to Claim 26 wherein said stoichiometric encapsulating layer is between about 1000 and 3000 angstroms thick.

33. A passivated semiconductor structure according to Claim 26 wherein said silicon carbide substrate is a single crystal having a polytype selected from the group consisting of the 3C, 4H, 6H, and 15Rpolytypes of silicon carbide.

34. A method of passivating wide bandgap devices, the method comprising:
sputter-depositing a non-stoichiometric nitride layer selected from the group consisting of silicon nitride and aluminum nitride on a layer of semiconductor material selected from the group consisting of silicon carbide and the Group III nitrides; and
depositing an environmental barrier layer of stoichiometric silicon nitride by chemical vapor deposition on to the sputter-deposited layer.

35. A method according to Claim 34 comprising sputtering a silicon target in a substantially hydrogen-free environment.

36. A method according to Claim 35 comprising sputtering the silicon target in an environment of argon and nitrogen.

37. A method according to Claim 36 comprising sputtering with a pulsed direct current power source to thereby discharge insulating particles while avoiding arcing.

38. A method according to Claim 34 comprising sputtering at room temperature.

39. A method of according to Claim 34 comprising sputtering while elevating the substrate temperature, while avoiding exceeding temperatures that would otherwise detrimentally affect the remainder of the device.

40. A method according to claim 39 comprising elevating the substrate temperature to between about 350 0C and 450 0C.

41. A method according to Claim 34 comprising sputtering in a nitrogen-rich environment to provide a non-stoichiometric silicon nitride.

42. A method according to Claim 34 wherein the step of depositing the environmental barrier layer further comprises sputter depositing at least one
stoichiometric silicon nitride layer.

43. A method according to Claim 34 comprising applying a radio frequency bias to the substrate during the sputtering step to generate an ion bombardment.

44. A method according to Claim 34 comprising lowering the ambient pressure during the sputtering step to generate an ion bombardment.

45. A method according to Claim 34 further comprising:
thermally oxidizing a silicon carbide substrate; and
annealing the thermal oxide in a nitrogen-oxide composition;
both prior to the step of sputter-depositing the non-stoichiometric SiC layer.

46. A method according to Claim 45 comprising annealing the thermal oxide in N2O or in NO.