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1. WO2006113061 - CELLULE-SOI 6T-SRAM DE SUBSTRAT HYBRIDE POUR UNE STABILITE ET UNE PERFORMANCE DE CELLULE AMELIOREE

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CLAIMS

What is claimed is:

1. A 6T-SRAM cell semiconducting structure comprising:

a substrate comprising an SOI region and a bulk-Si region, wherein said SOI region and said bulk-Si region have a same or differing crystallographic orientation;

an isolation region separating said SOI region from said bulk-Si region;

a well region underlying a device in said bulk-Si region and a contact to said well region, wherein said contact stabilizes floating body effects and provides a means for adjusting the threshold voltages in FETs in the bulk-Si region through the application of a bias voltage; and

a device configuration selected from the group consisting of (a) two pass-gate nFET devices located in the bulk-Si region and two pull-down nFET devices and two pull-up pFET devices located in the SOI region, (b) two pass-gate nFET devices and two-pull down nFET devices located in the bulk-Si region and two pull-up pFET devices located in the SOI region, (c) two pull-down nFET devices located in the bulk-Si region and two pass-gate nFET devices and two pull-up pFET devices located in the SOI region and (d) two pull-up pFET devices located in the bulk-Si region and a pull-down nFET and a pass-gate nFET located in the SOI region.

2. The 6T-SRAM cell semiconducting structure of Claim 1 wherein device configuration (a) is present.

3. The 6T-SRAM cell semiconducting structure of Claim 2 wherein said bulk-Si region and said SOI region have the same crystal orientation.

4. The 6T-SRAM cell semiconducting structure of Claim 3 wherein said same crystal orientation is (100).

5. The 6T-SRAM cell semiconducting structure of Claim 2 wherein said bulk-Si region and said SOI region have different crystal orientations.

6. The 6T-SRAM cell semiconducting structure of Claim 5 wherein said different crystal orientations comprise (100), (110) or (111).

7. The 6T-SRAM cell semiconducting structure of Claim 2 wherein said bulk-Si region and said SOI region comprise the same or different semiconductor material.

8. The 6T-SRAM cell semiconducting structure of Claim 7 wherein said semiconductor material is a Si-containing semiconductor material.

9. The 6T-SRAM cell semiconducting structure of Claim 1 wherein device configuration (b) is present.

10. The 6T-SRAM cell semiconducting structure of Claim 9 wherein said bulk-Si region and said SOI region have the same crystal orientation.

11. The 6T-SRAM cell semiconducting structure of Claim 10 wherein said same crystal orientations is (100).

12. The 6T-SRAM cell semiconducting structure of Claim 9 wherein said bulk-Si region and said SOI region have different crystal orientations.

13. The 6T-SRAM cell semiconducting structure of Claim 12 wherein said different crystal orientation comprise (100), (110) or (111).

14. The 6T-SRAM cell semiconducting structure of Claim 9 wherein said bulk-Si region and said SOI region comprise the same or different semiconductor material.

15. The 6T-SRAM cell semiconducting structure of Claim 14 wherein said semiconductor material is a Si-containing semiconductor material.

16. The 6T-SRAM cell semiconducting structure of Claim 1 wherein device configuration (c) is present.

17. The 6T-SRAM cell semiconducting structure of Claim 16 wherein said bulk-Si region and said SOI region have the same crystal orientation.

18. The 6T-SRAM cell semiconducting structure of Claim 17 wherein said same crystal orientation is (100).

19. The 6T-SRAM cell semiconducting structure of Claim 16 wherein said bulk-Si region and said SOI region have different crystal orientations.

20. The 6T-SRAM cell semiconducting structure of Claim 19 wherein said different crystal orientations comprise (100), (110) or (111).

21. The 6T-SRAM cell semiconducting structure of Claim 16 wherein said bulk-Si region and said SOI region comprise the same or different semiconductor material.

22. The 6T-SRAM cell semiconducting structure of Claim 21 wherein said semiconductor material is a Si-containing semiconductor material.

23. The 6T-SRAM cell semiconducting structure of Claim 1 wherein device configuration (d) is present.

24. The 6T-SRAM cell semiconducting structure of Claim 23 wherein said bulk-Si region and said SOI region have the same crystal orientation.

25. The 6T-SRAM cell semiconducting structure of Claim 24 wherein said same crystal orientation is (100).

26. The 6T-SRAM cell semiconducting structure of Claim 23 wherein said bulk-Si region and said SOI region have different crystal orientations.

27. The 6T-SRAM cell semiconducting structure of Claim 26 wherein said different crystal orientations comprise ( 100), ( 110) or ( 111 ) .

28. The 6T-SRAM cell semiconducting structure of Claim 23 wherein said bulk-Si region and said SOI region comprise the same or different semiconductor material.

29. The 6T-SRAM cell semiconducting structure of Claim 28 wherein said semiconductor material is a Si-containing semiconductor material.

30. A semiconductor structure comprising:

a 6T-SRAM cell located on a hybrid substrate, said hybrid substrate comprising an SOI region and a bulk-Si region, wherein said SOI region and said bulk-Si region have a same or different crystallographic orientation; and a well region underlying a device in said bulk-Si region and a contact to said well region, wherein said contact stabilizes floating body effects and provides a means for adjusting threshold voltages in FETs in the bulk-Si region through application of a bias voltage.

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