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1. (WO2003088500) SELECTABLE CLOCKING ARCHITECTURE
Dernières données bibliographiques dont dispose le Bureau international   

N° de publication :    WO/2003/088500    N° de la demande internationale :    PCT/US2003/009627
Date de publication : 23.10.2003 Date de dépôt international : 27.03.2003
Demande présentée en vertu du Chapitre 2 :    25.09.2003    
CIB :
H03M 9/00 (2006.01), H04L 7/02 (2006.01), H04L 25/05 (2006.01)
Déposants : INTEL CORPORATION [US/US]; (a Delawere Corporation), 2200 Mission College Boulevard, Santa Clara, CA 95052 (US)
Inventeurs : FAGERHOEJ, Thomas; (NL)
Mandataire : TROP, Timothy, N.; Trop, Pruner & Hu, P.C., 8554 Katy Freeway, Suite 100, Houston, TX 77024 (US)
Données relatives à la priorité :
10/117,702 05.04.2002 US
Titre (EN) SELECTABLE CLOCKING ARCHITECTURE
(FR) SELECTABLE CLOCKING ARCHITECTURE
Abrégé : front page image
(EN)A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit (54) and providing a second clock signal to a memory (52) storing data for conversion by the conversion circuit. One of the first and second clock signals is selectively synchronized to a reference clock signal. The other clock is synchronized to said first or second clock. The synchronization circuit can be selectively place in a first operational mode, to synchronize the first clock to the reference clock or in a second operational mode, to synchronize the second clock to the reference clock.
(FR)A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit (54) and providing a second clock signal to a memory (52) storing data for conversion by the conversion circuit. One of the first and second clock signals is selectively synchronized to a reference clock signal. The other clock is synchronized to said first or second clock. The synchronization circuit can be selectively place in a first operational mode, to synchronize the first clock to the reference clock or in a second operational mode, to synchronize the second clock to the reference clock.
États désignés : AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NI, NO, NZ, OM, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW.
Organisation régionale africaine de la propriété intellectuelle (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Office eurasien des brevets (OEAB) (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
Office européen des brevets (OEB) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR)
Organisation africaine de la propriété intellectuelle (OAPI) (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Langue de publication : anglais (EN)
Langue de dépôt : anglais (EN)